SY69952

2

Micrel

RSER

Recovered Serial Data. These Positive ECL 100K outputs

(+5V referenced) represent the recovered data from the

input data stream (RIN

±). This recovered data is aligned

with the recovered clock (RCLK

±) with a sampling window

compatible with most data processing devices.

RCLK

Recovered Clock. These Positive ECL 100K outputs (+5V

referenced) represent the recovered clock from the input

data stream (RIN

±). This recovered clock is used to sample

the recovered data (RSER

±) and has timing compatible

with most data processing devices.

LFI – TTL Output

Link Fault Indicator. This input indicates the status of the

input data stream (RIN

±). It is controlled by three functions;

the Carrier Detect (CD) input, the internal Transition Detector,

and the Out of Lock (OOL) detector. The Transition Detector

determines if RIN

± contains enough transitions to be

accurately recovered by the Receive PLL. The Out of Lock

detector determines if RIN

± is within the frequency range of

the Receive PLL. When CD is HIGH and RIN

± has sufficient

transitions and is within the frequency range of the Receive

PLL, the LFI input will be high. If CD is at an ECL LOW or

RIN

± does not contain sufficient transitions or RIN± is outside

the frequency range of the Receive PLL then the LFI output

will be LOW. If CD is at a TTL LOW then the LFI output will

only transition LOW when the frequency of RIN

± is outside

the range of the Receive PLL.

TOUT

Transmit Output. These Positive ECL 100K outputs (+5V

referenced) represent the buffered version of the Transmit

data stream (TSER

±). This Transmit path is used to take

weak input signals and rebuffer them to drive low impedance

copper media.

TCLK

Transmit Clock. These Positive ECL 100K outputs (+5V

referenced) provide the bit rate frequency source for external

Transmit data processing devices. This output is synthesized

by the Transmit PLL and is derived by multiplying the

REFCLK frequency by eight.

LOOP – TTL Input

Loop Back Select. This input is used to select the input

data stream source that the Receive PLL used for clock

and data recovery. When the LOOP input is HIGH, the

Receive input data stream (RIN

±) is used for clock and

data recovery. When LOOP is LOW, the Transmit input

data stream (TSER

±) is used by the Receive PLL for clock

and data recovery.

INPUTS

RIN

Receive Input. These built-in line receiver inputs are

connected to the differential Receive serial input data stream.

An internal Receive PLL recovers the embedded clock

(RCLK

±) and data (RSER±) information. The incoming data

rate can be within one of two frequency ranges depending

on the state of the MODE pin.

CD – PECL/TTL Input

Carrier Detect. This input controls the recovery function

of the Receive PLL and can be driven by the carrier detect

output from optical modules or from external transition

detection circuitry. When this input is at an ECL HIGH, the

input data stream (RIN

±) is recovered normally by the

Receive PLL. When this input is at an ECL LOW, the

Receive PLL no longer aligns to RIN

±, but instead aligns

with the REFCLKx8 frequency. Also, the Link Fault Indicator

(LFI) will transition LOW, and the recovered data outputs

(RSER) will remain LOW regardless of the signal level on

the Receive data stream inputs (RIN). When the CD input

is at a TTL LOW (

≤0.8V), the internal transition detection

circuitry is disabled.

TSER

Transmit Serial Data. These built-in line receiver inputs

are connected to the differential Transmit serial input data

stream. These inputs can receive very low amplitude signals

and are compatible with all PECL signal levels.

REFCLK

Reference Clock. This input is the clock frequency

reference for the clock and data recovery Receive PLL.

REFCLK is multiplied internally by eight and sets the

approximate center frequency for the internal Receive PLL

to track the incoming bit stream. This input is also multiplied

by eight by the frequency multiplier Transmit PLL to produce

the bit rate Transmit Clock (TCLK

±). REFCLK can be

connected to either a differential PECL or single-ended TTL

frequency source. When either REFCLK+ or REFCLK- is at

a TTL LOW, the opposite REFCLK signal becomes a TTL

level input.

OUTPUTS

ROUT

Receive Output. These Positive ECL 100K outputs (+5V

referenced) represent the buffered version of the input data

stream (RIN

±). This output pair can be used for Receiver

input data equalization in copper based systems, reducing

the system impact of data dependent jitter. All PECL outputs

can be powered down by connecting both outputs to VCC

or leaving them both unconnected.

PIN DESCRIPTIONS