SY69952

4

Micrel

DESCRIPTION

The Transmit PECL differential input pair (TSER

±) is

buffered by the SY69952 yielding the differential data outputs

(TOUT

±). These outputs can be used to directly drive

transmission media such as Printed Circuit Board (PCB)

traces, optical drivers, twisted pair, or coaxial cable.

Receive Functions

The primary function of the receiver is to recover clock

(RCLK

±) and data (RSER±) from the incoming differential

PECL data stream (RIN

±) without the need for external

buffering. These built-in line receiver inputs, as well as the

TSER

± inputs mentioned above, have a wide common-

mode range (2.5V) and the ability to receive signals with as

little as 50mV differential voltage. They are compatible with

all PECL signals and any copper media.

The clock recovery function is performed using an

embedded PLL. The recovered clock is not only passed to

the RCLK

± outputs, but also used internally to sample the

input serial stream in order to recover the data pattern. The

Receive PLL uses the REFCLK input as a byte-rate

reference. This input is multiplied by 8 (REFCLKx8) and is

used to improve PLL lock time and to provide a center

frequency for operation in the absence of input data stream

transitions. The receiver can recover clock and data in two

different frequency ranges depending on the state of the

MODE pin as explained earlier. To insure accurate data

and clock recovery, REFCLKx8 must be within 1000 ppm of

the transmit bit rate. The standards, however, specify that

the REFCLKx8 frequency accuracy be within 20-100 ppm.

The differential input serial data (RIN

±) is not only used

by the PLL to recover the clock and data, but it is also

buffered and presented as the PECL differential output pair

ROUT

±. This output pair can be used as part of the

transmission line interface circuit for base line wander

compensation, improving system performance by providing

reduced input jitter and increased data eye opening.

Carrier Detect and Link Fault Indicator Functions

The Link Fault Indicator (LFI) output is a TTL-level output

that indicates the status of the receiver. This output can

used by an external controller for Loss of Signal (LOS),

Loss of Frame (LOF), or Out of Frame (OOF) indications.

LFI is controlled by the Carrier Detect input, the internal

Transitions Detector, and the PLL Out of Lock (OOL)

circuitry.

The CD input may be driven by external circuitry that is

monitoring the incoming data stream. Optical modules have

CD outputs that indicate the presence of light on the optical

fiber and some copper based systems use external threshold

detection circuitry to monitor the incoming data stream. The

CD input is a 100K PECL compatible signal that should be

held HIGH when the incoming data stream is valid. When

CD is pulled to a PECL LOW (

≤2.5V max.), the LFI output

will transition LOW and the Receiver PLL will align itself

with the REFCLKx8 frequency and the recovered data

outputs (RSER) will remain LOW regardless of the signal

level on the Receive data-stream inputs (RIN).

In addition, the SY69952 has a built-in transitions detector

that also checks the quality of the incoming data stream.

The absence of data transitions can be caused by a broken

transmission media, a broken transmitter, or a problem with

the transmit or receive media coupling. The SY69952 will

detect a quiet link by counting the number of bit times that

have passed without a data transition. A bit time is defined

as the period of RCLK

±. When 512 bit times have passed

without a data transition on RIN

±, LFI will transition LOW.

The receiver will assume that the serial data stream is invalid

and, instead of allowing the RCLK

± frequency to wander in

the absence of data, the PLL will lock to the REFCLKx8

frequency. This will insure that RCLK

± is as close to the

correct link operating frequency as the REFCLK accuracy.

LFI will be driven HIGH again and the receiver will recover

clock and data from the incoming data stream when the

transition detection circuitry determines that adequate

transitions to ensure reliable clock and data recovery have

been detected within 512 bit-times.

The Transition Detector can be turned off by pulling the

CD input to a TTL LOW (

≤0.8V). When CD is pulled to a

TTL LOW the LFI will only be driven LOW if the recovered

clock is not locked to the incoming data stream. LFI LOW in

this will only indicate that the Receiver PLL is Out of Lock

(OOL). The CD pin should not be left unconnected.

Loop Back Testing

The TTL level LOOP pin is used to perform loop-back

testing. When LOOP is asserted (held LOW) the Transmitter

serial input (TSER

±) is used by the Receiver PLL for clock

and data recovery. This allows in-system testing to be

performed on the entire device except for the differential

Transmit drivers (TOUT

±) and the differential Receiver inputs

(RIN

±). For example, an ATM controller can present ATM

cells to the input of the ATM cell processor and check to

see that these same cells are received. When the LOOP

input is deasserted (held HIGH) the Receive PLL is once

again connected to the Receiver serial inputs (RIN

±).

The LOOP feature can also be used in applications where

clock and data recovery are to be performed from either of

two data streams. In these systems the LOOP pin is used

to select whether the TSER

± or the RIN± inputs are used

by the Receive PLL for clock and data recovery. In the

Loop back testing mode, regardless of the presence of data

at the input (RIN

±), the transmit serial data stream from

(TSER

±) will flow through the Receive PLL to the Recovered

serial data output (RSER

±).