24LCS52

DS21166B-page 8

Preliminary

© 1996 Microchip Technology Inc.

7.4

Contiguous Addressing Across

Multiple Devices

The chip select bits A2, A1, A0 can be used to expand

the contiguous address space for up to 16K bits by add-

ing up to eight 24LCS52 devices on the same bus. In

this case, software can use A0 of the control byte as

address bit A8, A1 as address bit A9, and A2 as

address bit A10. It is not possible to sequentially read

across device boundaries.

8.0

PIN DESCRIPTIONS

8.1

SDA Serial Address/Data Input/Output

This is a bi-directional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pull-up

Ω for 100 kHz, 1kΩ for 400

kHz).

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are reserved

for indicating the START and STOP conditions.

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

8.3

A0, A1, A2

The levels on these inputs are compared with the cor-

responding bits in the slave address. The chip is

selected if the compare is true.

Up to eight 24LCS52 devices may be connected to the

same bus by using different chip select bit combina-

tions. These inputs must be connected to either Vcc or

Vss.

8.4

WP

This is the hardware write protect pin. It can be tied to

write protection is enabled. If the WP pin is tied to Vss

the hardware write protection is disabled. If the WP pin

is left floating, an internal pull down resistor will pull the

WP pin to Vss and the hardware write protection will be

disabled.

8.5

Noise Protection

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.