© 1996 Microchip Technology Inc.

Preliminary

DS21166B-page 1

FEATURES

• Single supply with operation down to 2.5V

• Low power CMOS technology

- 1 mA active current typical

- 10

µA standby current typical at 5.5V

-5

µA standby current typical at 3.0V

• Organized as a single block of 256 bytes (256 x 8)

• Software write protection for lower 128 bytes

• Hardware write protection for entire array

™ compatible

• 100kHz (2.5V) and 400kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 16 bytes

• 3.5 ms typical write cycle time for page-write

• 10,000,000 erase/write cycles guaranteed

• ESD protection >4,000V

• Data retention > 200 years

• 8-pin DIP, SOIC or TSSOP packages

• Available for extended temperature ranges

DESCRIPTION

The Microchip Technology Inc. 24LCS52 is a 2K bit

Electrically Erasable PROM capable of operation

across a broad voltage range (2.5V to 5.5V). This

device has a software write protect feature for the lower

half of the array, as well as an external pin that can be

used to write protect the entire array. The software write

protect feature is enabled by sending the device a spe-

cial command, and once this feature has been enabled,

it cannot be reversed. In addition to the software pro-

tect feature, there is a WP pin that can be used to write

protect the entire array, regardless of whether the soft-

ware write protect register has been written or not. This

allows the system designer to protect none, half or all of

the array, depending on the application. The device is

organized as a single block of 256 x 8-bit memory with

a 2-wire serial interface. Low voltage design permits

operation down to 2.5 volts with typical standby and

active currents of only 5

µA and 1 mA respectively. The

device has a page-write capability for up to 16 bytes of

data. The device is available in the standard 8-pin DIP,

8-pin SOIC and TSSOP packages.

- Commercial (C):

0

°C to +70°C

- Industrial (I):

-40

°C to +85°C

PACKAGE TYPES

BLOCK DIAGRAM

PDIP/SOIC

TSSOP

A0

A1

A2

Vss

Vcc

WP

SCL

SDA

1

2

3

4

8

7

6

5

Vcc

WP

SCL

SDA

A0

A1

A2

Vss

1

2

3

4

8

7

6

5

I/O

Control

Logic

Memory

Control

Logic

XDEC

HV Generator

Standard

Array

Software write

Write Protect

Circuitry

YDEC

Vcc

Vss

SENSE AMP

R/W CONTROL

SDA SCL

A0 A1 A2

WP

protected area

(00h-7Fh)

24LCS52

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