PIC876 datasheet(81/218 Pages) MICROCHIP

81 / 218 page

 2001 Microchip Technology Inc.

DS30292C-page 79

PIC16F87X

9.2.7

I2C MASTER MODE SUPPORT

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON and by setting the

SSPEN bit. Once Master mode is enabled, the user

has six options:

• Assert a START condition on SDA and SCL.

• Assert a Repeated START condition on SDA and

SCL.

• Write to the SSPBUF register initiating transmis-

sion of data/address.

• Generate a STOP condition on SDA and SCL.

• Configure the I2C port to receive data.

• Generate an Acknowledge condition at the end of

a received byte of data.

9.2.7.1

I2C Master Mode Operation

The master device generates all of the serial clock

pulses and the START and STOP conditions. A trans-

fer is ended with a STOP condition or with a Repeated

START condition. Since the Repeated START condi-

tion is also the beginning of the next serial transfer, the

I2C bus will not be released.

In Master Transmitter mode, serial data is output through

SDA, while SCL outputs the serial clock. The first byte

transmitted contains the slave address of the receiving

device (7 bits) and the Read/Write (R/W) bit. In this case,

the R/W bit will be logic '0'. Serial data is transmitted 8 bits

at a time. After each byte is transmitted, an Acknowledge

bit is received. START and STOP conditions are output

to indicate the beginning and the end of a serial transfer.

In Master Receive mode, the first byte transmitted con-

tains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic '1'. Thus, the first byte transmitted is a 7-bit slave

address followed by a '1' to indicate receive bit. Serial

data is received via SDA, while SCL outputs the serial

clock. Serial data is received 8 bits at a time. After each

byte is received, an Acknowledge bit is transmitted.

START and STOP conditions indicate the beginning

and end of transmission.

The baud rate generator used for SPI mode operation

is now used to set the SCL clock frequency for either

100 kHz, 400 kHz, or 1 MHz I2C operation. The baud

rate generator reload value is contained in the lower 7

bits of the SSPADD register. The baud rate generator

will automatically begin counting on a write to the

SSPBUF. Once the given operation is complete (i.e.,

transmission of the last data bit is followed by ACK), the

internal clock will automatically stop counting and the

SCL pin will remain in its last state.

A typical transmit sequence would go as follows:

User generates a START condition by setting

the START enable bit (SEN) in SSPCON2.

SSPIF is set. The module will wait the required

start time before any other operation takes place.

User loads SSPBUF with address to transmit.

Address is shifted out the SDA pin until all 8 bits

are transmitted.

MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

MSSP module generates an interrupt at the end

of the ninth clock cycle by setting SSPIF.

User loads SSPBUF with eight bits of data.

DATA is shifted out the SDA pin until all 8 bits are

transmitted.

MSSP module shifts in the ACK bit from the

slave device, and writes its value into the

SSPCON2 register (SSPCON2<6>).

MSSP module generates an interrupt at the end

of the ninth clock cycle by setting the SSPIF bit.

User generates a STOP condition by setting the

STOP enable bit, PEN, in SSPCON2.

Interrupt is generated once the STOP condition

is complete.

9.2.8

BAUD RATE GENERATOR

In I2C Master mode, the reload value for the BRG is

located in the lower 7 bits of the SSPADD register

(Figure 9-10). When the BRG is loaded with this value,

the BRG counts down to 0 and stops until another reload

has taken place. The BRG count is decremented twice

per instruction cycle (TCY), on the Q2 and Q4 clock.

In I2C Master mode, the BRG is reloaded automatically. If

clock arbitration is taking place, the BRG will be reloaded

when the SCL pin is sampled high (Figure 9-11).

FIGURE 9-10:

BAUD RATE GENERATOR

BLOCK DIAGRAM

Note:

The MSSP Module, when configured in I2C

Master mode, does not allow queueing of

events. For instance, the user is not

allowed to initiate a START condition and

immediately write the SSPBUF register to

initiate transmission before the START

condition is complete. In this case, the

SSPBUF will not be written to and the

WCOL bit will be set, indicating that a write

to the SSPBUF did not occur.

Note:

Baud Rate = FOSC / (4 * (SSPADD + 1) )

SSPM3:SSPM0

BRG Down Counter

CLKOUT

FOSC/4

SSPADD<6:0>

SSPM3:SSPM0

SCL

Reload

Control

Reload

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