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PIC876 Datasheet(PDF) 18 Page - Microchip Technology |
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PIC876 Datasheet(HTML) 18 Page - Microchip Technology |
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18 / 218 page  PIC16F87X DS30292C-page 16 2001 Microchip Technology Inc. Bank 1 80h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19 82h(3) PCL Program Counter (PC) Least Significant Byte 0000 0000 26 83h(3) STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 18 84h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 27 85h TRISA — — PORTA Data Direction Register --11 1111 29 86h TRISB PORTB Data Direction Register 1111 1111 31 87h TRISC PORTC Data Direction Register 1111 1111 33 88h(4) TRISD PORTD Data Direction Register 1111 1111 35 89h(4) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 37 8Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26 8Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20 8Ch PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 21 8Dh PIE2 — (5) — EEIE BCLIE — — CCP2IE -r-0 0--0 23 8Eh PCON — — — — — — POR BOR ---- --qq 25 8Fh — Unimplemented — — 90h — Unimplemented — — 91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 68 92h PR2 Timer2 Period Register 1111 1111 55 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 73, 74 94h SSPSTAT SMP CKE D/A PS R/W UA BF 0000 0000 66 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 95 99h SPBRG Baud Rate Generator Register 0000 0000 97 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 116 9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 112 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page: Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. 3: These registers can be addressed from any bank. 4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’. 5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear. |
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