© 2002 Microchip Technology Inc.

DS21381B-page 5

TC1270/TC1271

3.0

APPLICATIONS INFORMATION

3.1

ing and reset timing during power-up, power-down, and

brownout/sag conditions, and rejects negative-going

transients (glitches) on the power supply line. Figure

3-1 shows the maximum transient duration vs.

maximum negative excursion (overdrive) for glitch

rejection. Any combination of duration and overdrive

that lays under the curve will not generate a reset

signal. Combinations above the curve are detected as

a brownout or power-down. Transient immunity can be

improved by adding a capacitor in close proximity to the

FIGURE 3-1:

MAXIMUM TRANSIENT

DURATION VS.

OVERDRIVE FOR GLITCH

REJECTION AT 25°C

3.2

RESET Signal Integrity During

Power-Down

Below this voltage the output becomes an "open

circuit" and does not sink current. This means CMOS

logic

inputs to

the

µPwill befloatingat an

undetermined

voltage.

Most

digital systems

are

completely

shut

down

well

above

this

voltage.

However, in

situations

where

RESET

must

be

be connected from RESET to ground to discharge stray

capacitances and hold the output low (Figure 3-2). This

resistor value, though not critical, should be chosen

such that it does not appreciably load RESET under

normal operation (100k

Ω will be suitable for most

required for the TC1271 to ensure a valid high RESET

FIGURE 3-2:

ENSURING RESET VALID

3.3

Processors With Bidirectional

I/O Pins

Some

µP's (such as Motorola 68HC11) have bi-

directional reset pins. Depending on the current drive

capability of the processor pin, an indeterminate logic

level may result if there is a logic conflict. This can be

avoided by adding a 4.7 k

Ω resistor in series with the

output of the TC1270/TC1271 (Figure 3-3). If there are

other components in the system which require a reset

signal, they should be buffered so as not to load the

reset line. If the other components are required to

follow the reset I/O of the

µP, the buffer should be

connected as shown with the solid line.

FIGURE 3-3:

INTERFACING TO

BIDIRECTIONAL

RESET I/O

RESET COMPARATOR OVERDRIVE,

400

240

160

320

80

0

1

10

100

1000

°C

Duration

Overdrive

TC127LMJ

TC127xR/S/T

TC1270

R1

100k

RESET

GND

TC1270

RESET

GND

RESET

GND

Buffered RESET

To Other System

Components

Buffer

µP

4.7k