16F628 datasheet(38/168 Pages) MICROCHIP

38 / 168 page

PIC16F627A/628A/648A

DS40044A-page 36

Preliminary

 2002 Microchip Technology Inc.

TABLE 5-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA(1)

5.2

PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The

corresponding data direction register is TRISB. A '1' in

the TRISB register puts the corresponding output driver

in a High-impedance mode. A '0' in the TRISB register

puts the contents of the output latch on the selected

pin(s).

PORTB is multiplexed with the external interrupt,

USART, CCP module and the TMR1 clock input/output.

The standard port functions and the alternate port func-

tions are shown in Table 5-3. Alternate port functions

may override TRIS setting when enabled.

Reading PORTB register reads the status of the pins,

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. So a write

to a port implies that the port pins are first read, then

this value is modified and written to the port data latch.

Each of the PORTB pins has a weak internal pull-up

(

≈200 µA typical). A single control bit can turn on all the

pull-ups.

This

done

clearing

the

RBPU

(OPTION<7>) bit. The weak pull-up is automatically

turned off when the port pin is configured as an output.

The pull-ups are disabled on Power-on Reset.

Four of PORTB’s pins, RB<7:4>, have an interrupt-on-

change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB<7:4> pin con-

figured as an output is excluded from the interrupt-on-

change comparison). The input pins (of RB7:RB4) are

compared with the old value latched on the last read of

PORTB. The “mismatch” outputs of RB7:RB4 are

OR’ed together to generate the RBIF interrupt (flag

latched in INTCON<0>).

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the

interrupt in the following manner:

Any read or write of PORTB. This will end the

mismatch condition.

Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit RBIF to be cleared.

This interrupt on mismatch feature, together with

software configurable pull-ups on these four pins allow

easy interface to a key pad and make it possible for

wake-up on key-depression. (See AN552)

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR

Value on

All Other

RESETS

05h

PORTA

RA7

RA6

RA5(2)

RA4

RA3

RA2

RA1

RA0

xxxx 0000

qqqu 0000

85h

TRISA

TRISA7

TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1

TRISA0

1111 1111

1Fh

CMCON

C2OUT

C1OUT

C2INV

C1INV

CIS

CM2

CM1

CM0

0000 0000

9Fh

VRCON

VREN

VROE

VRR

—

VR3

VR2

VR1

VR0

000- 0000

Legend:

— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: Shaded bits are not used by PORTA.

2: MCLRE Configuration Bit sets RA5 functionality.

Note:

If a change on the I/O pin should occur

when a read operation is being executed

(start of the Q2 cycle), then the RBIF inter-

rupt flag may not get set.

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