16F628 datasheet(99/168 Pages) MICROCHIP

99 / 168 page

 2002 Microchip Technology Inc.

Preliminary

DS40044A-page 97

PIC16F627A/628A/648A

14.2.8

SPECIAL FEATURE: DUAL SPEED

OSCILLATOR MODES

A software programmable dual speed Oscillator mode

is provided when the PIC16F627A/628A/648A is con-

figured in the INTOSC Oscillator mode. This feature

allows users to dynamically toggle the oscillator speed

between 4 MHz and 37 kHz nominal in the INTOSC

mode. Applications that require low current power sav-

ings, but cannot tolerate putting the part into SLEEP,

may use this mode.

There is a time delay associated with the transition

between Fast and Slow oscillator speeds. This Oscilla-

tor Speed Transition delay consists of two existing

clock pulses and eight new speed clock pulses. During

this Clock Speed Transition Delay the System Clock is

halted causing the processor to be frozen in time. Dur-

ing this delay the Program Counter and the Clock Out

stop.

The OSCF bit in the PCON register is used to control

Dual Speed mode. See Section 4.2.2.6, Register 4-6.

14.3

RESET

The PIC16F627A/628A/648A differentiates between

various kinds of RESET:

Power-on Reset (POR)

MCLR Reset during normal operation

MCLR Reset during SLEEP

WDT Reset (normal operation)

WDT wake-up (SLEEP)

Brown-out Reset (BOR)

Some registers are not affected in any RESET condi-

tion; their status is unknown on POR and unchanged in

any other RESET. Most other registers are reset to a

“RESET state” on Power-on Reset, Brown-out Reset,

MCLR Reset, WDT Reset and MCLR Reset during

SLEEP. They are not affected by a WDT wake-up,

since this is viewed as the resumption of normal oper-

ation. TO and PD bits are set or cleared differently in

different RESET situations as indicated in Table 14-4.

These bits are used in software to determine the nature

of the RESET. See Table 14-7 for a full description of

RESET states of all registers.

A simplified block diagram of the on-chip RESET circuit

is shown in Figure 14-6.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Table 17-7 for pulse width

specification.

FIGURE 14-6:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

RESET

MCLR/

OSC1/

WDT

Module

DD rise

detect

OST/PWRT

WDT

Time out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple-counter

Reset

Enable OST

Enable PWRT

SLEEP

See Table 14-3 for time out situations.

Note

This is a separate oscillator from the INTOSC/RC oscillator.

Brown-out

detect Reset

BOREN

CLKIN

PP Pin

10-bit Ripple-counter

Schmitt Trigger Input

On-chip(1)

OSC

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