16F628 datasheet(101/168 Pages) MICROCHIP

101 / 168 page

 2002 Microchip Technology Inc.

Preliminary

DS40044A-page 99

PIC16F627A/628A/648A

14.4.5

TIME OUT SEQUENCE

On power-up the time out sequence is as follows: First

PWRT time out is invoked after POR has expired. Then

OST is activated. The total time out will vary based on

oscillator configuration and PWRTE bit STATUS. For

example, in RC mode with PWRTE bit set (PWRT dis-

abled), there will be no time out at all. Figure 14-8,

Figure 14-9

and

Figure 14-10

depict

time

out

sequences.

Since the time outs occur from the POR pulse, if MCLR

is kept low long enough, the time outs will expire. Then

bringing MCLR high will begin execution immediately

(see Figure 14-9). This is useful for testing purposes or

to synchronize more than one PIC16F627A/628A/

648A device operating in parallel.

Table 14-6 shows the RESET conditions for some spe-

cial registers, while Table 14-7 shows the RESET con-

ditions for all the registers.

14.4.6

POWER CONTROL (PCON) STATUS

The power control/STATUS register, PCON (address

8Eh) has two bits.

Bit0 is BOR (Brown-out Reset). BOR is unknown on

Power-on-Reset. It must then be set by the user and

checked on subsequent RESETS to see if BOR = 0

indicating that a brown-out has occurred. The BOR

STATUS bit is a don’t care and is not necessarily

predictable if the brown-out circuit is disabled (by

setting BOREN bit = 0 in the Configuration word).

Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a subse-

quent RESET if POR is ‘0’, it will indicate that a Power-

on Reset must have occurred (V

DD may have gone too

low).

TABLE 14-3:

TIME OUT IN VARIOUS SITUATIONS

TABLE 14-4:

STATUS/PCON BITS AND THEIR SIGNIFICANCE

Oscillator Configuration

Power-up

Brown-out Reset

Wake-up

from SLEEP

PWRTEN = 0

PWRTEN = 1

PWRTEN = 0

PWRTEN = 1

XT, HS, LP

72 ms +

1024•T

OSC

1024•T

OSC

72 ms +

1024•T

OSC

1024•T

OSC

1024•T

OSC

RC, EC

72 ms

—

72 ms

——

INTOSC

72 ms

—

72 ms

—

µs

POR

BOR

Condition

0X11

Power-on Reset

0X0X

Illegal, TO is set on POR

0XX0

Illegal, PD is set on POR

10XX

Brown-out Reset

110u

WDT Reset

1100

WDT Wake-up

11uu

MCLR Reset during normal operation

1110

MCLR Reset during SLEEP

Legend: u = unchanged, x = unknown.

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