LM5019_15 datasheet(22/30 Pages) TI

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UVLO

RON

RTN

VIN

BST

VCC

Power

PAD-8

CIN

CVCC

LM5019

SNVS788F – JANUARY 2012 – REVISED DECEMBER 2014

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9 Power Supply Recommendations

LM5019 is a power management device. The power supply for the device is any DC voltage source within the

specified input range.

10 Layout

10.1 Layout Guidelines

A proper layout is essential for optimum performance of the circuit. In particular, the following guidelines should

be observed:

1. CIN: The loop consisting of input capacitor (CIN), VIN pin, and RTN pin carries switching currents. Therefore,

the input capacitor should be placed close to the IC, directly across VIN and RTN pins and the connections to

these two pins should be direct to minimize the loop area. In general it is not possible to accommodate all of

input capacitance near the IC. A good practice is to use a 0.1-

μF or 0.47-μF capacitor directly across the VIN

and RTN pins close to the IC, and the remaining bulk capacitor as close as possible (see Figure 23).

2. CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high and

low side gate drivers. These two capacitors should also be placed as close to the IC as possible, and the

connecting trace length and loop area should be minimized (see Figure 23).

3. The Feedback trace carries the output voltage information and a small ripple component that is necessary for

proper operation of LM5019. Therefore, care should be taken while routing the feedback trace to avoid

coupling any noise to this pin. In particular, feedback trace should not run close to magnetic components, or

parallel to any other switching trace.

4. SW trace: The SW node switches rapidly between VIN and GND every cycle and is therefore a possible

source of noise. The SW node area should be minimized. In particular, the SW node should not be

inadvertently connected to a copper plane or pour.

10.2 Layout Example

Figure 23. Placement of Bypass Capacitors

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