3

ML6510

PIN DESCRIPTION

PIN NUMBER

NAME

DESCRIPTION

32

ROMMSB

MSB of the internal ROM address. Tie to GND if not used. See section on

Programming the ML6510.

20

Programming pin. See section on Programming the ML6510.

19

Programming pin. See section on Programming the ML6510.

21

MCLK

Programming pin. See section on Programming the ML6510.

22

RESET

Reset all internal circuits. Asserted polarity is low.

23

LOCK

Indicates when the PLL and deskew buffers have locked. Asserted polarity is

high.

28

29

Input clock type is selected by the CS bit in the shift register.

16,14,9,7,

CLK[0–7]

Clock outputs

44, 42, 37, 35

18,12,11,5,

FB[0–7]

Clock feedback inputs for the deskew buffers

2, 40, 39, 33

3,31

AVCC[1–3]

Analog circuitry supply pins, separated from noisy digital supply pins to

25

provide isolation. All supplies are nominally +5V.

4, 30, 24

AGND[1–3]

Analog circuitry ground pins

15

DVCC01

Digital supply pin for CLK0 and CLK1 output buffers. Nominally +5V.

8

DVCC23

Digital supply pin for CLK2 and CLK3 output buffers. Nominally +5V.

43

DVCC45

Digital supply pin for CLK4 and CLK5 output buffers. Nominally +5V.

36

DVCC67

Digital supply pin for CLK6 and CLK7 output buffers. Nominally +5V.

17, 13, 10, 6,

DGND[0–7]

Digital ground pins for CLK [0–7] output buffers. Each clock output buffer has

1, 41, 38, 34

its own ground pin to avoid crosstalk and ground bounce problems.

26

RCLKL

Differential reference clock output used to minimize

27

RCLKH

part-to-part skew when building clock trees with other PACMan

integrated circuits.