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ML6510 Datasheet(PDF) 11 Page - Micro Linear Corporation |
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ML6510 Datasheet(HTML) 11 Page - Micro Linear Corporation |
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11 / 18 page ![]() 11 ML6510 PCB trace impedance Z0 = 40Ω to 65Ω Lumped CL ≤ 20pF FBX CLKX ML6510-130 FIRST-ORDER MATCHED LOADS ML6510-130 GENERIC LOAD R2 One way trip delay < tRANGE/2 PCB trace impedance Z0 = 40Ω to 65Ω Lumped CLX ≤ 20pF FBX CLKX LOAD LOAD R2 R3 Length LX PCB trace impedance Z0 = 40Ω to 65Ω Lumped CLY ≤ 20pF FBY CLKY LOAD R2 R3 One way trip delay < tRANGE/2 Length LY |CLX – CLY| < 5pF |LX – LY| < 4" ZOX = ZOY R3 PCB trace impedance Z0 = 40Ω to 65Ω Lumped CL ≤ 20pF FBX CLKX ML6510-80 FIRST-ORDER MATCHED LOADS ML6510-80 GENERIC LOAD R1 One way trip delay < tRANGE/2 PCB trace impedance Z0 = 40Ω to 65Ω Lumped CLX ≤ 20pF FBX CLKX LOAD LOAD R1 Length LX PCB trace impedance Z0 = 40Ω to 65Ω Lumped CLY ≤ 20pF FBY CLKY LOAD R1 One way trip delay < tRANGE/2 Length LY |CLX – CLY| < 5pF |LX – LY| < 4" ZOX = ZOY EXTERNAL INPUT CLOCKS The external input clock to the ML6510 can be either a differential Pseudo-ECL clock or a single-ended TTL clock. This is selected using the CS bit in the serial shift register. For the single-ended TTL clock tie the CLKINH and CLKINL pins together. The ML6510 ensures that there is a well- defined phase difference between the input and output clocks. RESET AND LOCK When RESET is de-asserted, the internal programming logic will become active, loading in the configuration bits (see Programming the ML6510). Once the configuration is loaded, the PLL will lock onto the reference signal, and then the deskew blocks will adapt to the load conditions. When all eight output clocks are stable and deskewed, LOCK will be asserted. The asserted polarity of lock is high. Thus, LOCK can be used to indicate that the system is ready, or it can be used to drive the RESET input of another PACMan in a clock tree. CHIP VCC RESET LOCK tRESET tLOCK tLOCK PROGRAM IN THE CONFIGURATION PROGRAM IN THE CONFIGURATION 0 5V RESET may be reasserted at any time to reset the chip operations. Following a RESET assertion of valid pulse width (see Programming Electrical Characteristics), the ML6510 must again be loaded with a configuration, then it will re-lock and reassert lock when all eight clock outputs are stable and deskewed. |
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