ML6698

3

PIN

NAME

DESCRIPTION

1

(39)

AGND1

Analog ground.

2-6

(40-44)

TSM<4:0>

Transmit data TTL inputs. TSM<4:0> inputs accept TX data symbols. Data

appearing at TSM<4:0> are clocked into the ML6698 on the rising edge of TXC.

7

(1)

PWRDN

Device power down input. A low signal powers down all ciruits of the ML6698, and

dissipates less than 20mA.

8,9,

(2, 3,

RSM<4:0>

Receive data TTL outputs. RSM<4:0> outputs may be sampled synchronously with

11,13, 5, 7, 9)

RXC’s rising edge.

15

10

(4)

DGND1

Digital ground.

12

(6)

DVCC1

Digital +5V power supply.

14

(8)

DGND2

Digital ground.

16

(10)

RXC

Recovered receive symbol clock TTL output. This 25MHz clock is phase-aligned

with the internal 125MHz bit clock recovered from the signal received at TPINP/N

when data is present. Receive data at RSM<4:0> change on the falling edges and

should be sampled on the rising edges of this clock. RXC is phase aligned to TXC

when 100BASE-TX signal is not present at TPINP/N

17

(11)

DGND3

Digital ground.

18

(12)

DVCC2

Digital +5V power supply.

19

(13)

DGND4A

Digital ground.

20

(14)

DGND4B

Digital ground.

21

(15)

DGND4C

Digital ground.

22

(16)

DVCC5

Digital +5V power supply.

23

(17)

DGND5

Digital ground.

24

(18)

SD0

Signal detect TTL output. A high output level indicates 100BASE-TX activity at

TPINP/N with an amplitude exceeding the preset threshold. The signal detect

function is always active independent of the configuration of the SEL100/10 pin.

25

(19)

SEL100/10

Speed select TTL input. Driving this pin low disables 100BASE-TX transmit and

receive functions, and enables the 10BASE-T transmit path from 10BTTXINP/N to

TPOUTP/N. A high signal on SEL100/10 disables the 10BTTXINP/N inputs and enables

100BASE-TX operation.

28

(22)

AVCC3

Analog positive power supply.

30

(24)

RGMSET

Equalizer bias resistor input. An external 9.53ký, 1% resistor connected between

RGMSET and AGND3 sets internal time constants controlling the receive equalizer

transfer function.

31

(25)

RTSET

Transmit level bias resistor input. An external 2.49ký, 1% resistor connected

between RTSET and AGND3 sets a precision constant bias current for the twisted

pair transmit level.

32

(26)

AGND3

Analog ground.

33,34 (27,28)

TPOUTN/P

Transmit twisted pair outputs. This differential current output pair drives MLT-3

waveforms into the network coupling transformer in 100BASE-TX mode, and

10BASE-T or FLP waveforms in 10BASE-T mode.

35

(29)

AGND2

Analog ground.

36

(30)

AVCC2

Analog +5V power supply.

37,38 (31, 32)

TPINN/P

Receive twisted pair inputs. This differential input pair receives 100BASE-TX signals

from the network.