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ML6698 Datasheet(PDF) 1 Page - Micro Linear Corporation |
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ML6698 Datasheet(HTML) 1 Page - Micro Linear Corporation |
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1 / 12 page ![]() May 1997 ML6698* 100BASE-TX Physical Layer with 5-Bit Interface 1 GENERAL DESCRIPTION The ML6698 is a high-speed physical layer transceiver that provides a 5-bit (or symbol) interface to unshielded twisted pair cable media. The ML6698 is well suited for adapter card applications using the DEC 21143, the Macronix MX98713, or equivalent Media Access Controllers (MACs). The ML6698 may be used in other 100BASE-TX applications requiring the 5-bit interface as well as FDDI-over-copper applications. The ML6698 integrates 125MHz clock recovery/ generation, receive adaptive equalization, baseline wander correction and MLT-3/10BASE-T transmitter. FEATURES s 5-bit (or symbol) parallel interface s Compliant to IEEE 802.3u 100BASE-TX standard s Compliant to ANSI X3T12 TP-PMD (FDDI) standard s Single-jack 10BASE-T/100BASE-TX solution when used with external 10Mbps PHY s 125MHz receive clock recovery/generation s Baseline wander correction s Adaptive equalization and MLT-3 encoding/decoding s Supports full-duplex operation *Some Packages Are End Of Life As Of August 1, 2000 BLOCK DIAGRAM (PLCC Pin Configuration) TXC TPOUTP TPOUTN NRZ TO NRZI AND NRZI TO MLT-3 ENCODER CLOCK AND DATA RECOVERY NRZI TO NRZ DECODER RTSET TSM4 TSM3 TSM2 TPINP TPINN CMREF RGMSET SDO TSM1 TSM0 RXC RSM4 RSM3 RSM2 RSM1 RSM0 CLOCK SYTHESIZER CONTROL LOGIC EQUALIZER BLW CORRECTION MLT-3 DECODER LOOPBACK MUX SERIALIZER DESERIALIZER 100BASE-TX/10BASE-T TWISTED PAIR DRIVER 44 41 40 34 33 31 38 37 39 30 24 7 42 25 2 3 4 5 6 16 8 9 11 13 15 |
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