LM4030 datasheet(12/20 Pages) TI

12 / 20 page

x 0.1

VREF

= Percent_Error

VERROR

x 10

VREF

= ppmERROR

VERROR

x 10

VREF

= VERROR

LM4030

SNVS552B – MARCH 2008 – REVISED APRIL 2013

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Bit error (1 bit) to voltage error (mV):

(5)

VREF is in volts (V), VERROR is in milli-volts (mV), and n is the number of bits.

mV to ppm error in output voltage:

where

•

VREF is in volts (V) and VERROR is in milli-volts (mV)

(6)

Voltage error (mV) to percentage error (percent):

where

•

VREF is in volts (V) and VERROR is in milli-volts (mV)

(7)

PRINTED CIRCUIT BOARD and LAYOUT CONSIDERATIONS

The LM4030 has a very small change in reverse voltage with current (25ppm/mA typical) so large variations in

load current (up to 50mA) should not appreciably shift VREF. Parasitic resistance between the LM4030 and the

load introduces a voltage drop proportional to load current and should be minimized. The LM4030 should be

placed as close to the load it is driving as the layout will allow. The location of RZ is not important, but COUT

should be as close to the LM4030 as possible so added ESR does not degrade the transient performance.

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LM4030 Datasheet(PDF) 12 Page - Texas Instruments