CS

500 mV

LM5039

Peak Cycle-by-Cyle Limit

Average Current Limit

ACL

+

-

600 mV

Terminate

PWM

5V

5V

COMP

RAMP

PWM

COMPARATOR

Frequency

Foldback

Hiccup

Mode

Logic

12 PA

+5V

RES

22 PA

¹

·

©

500 mV

Rcs

x

LM5039

SNVS621D – FEBRUARY 2010 – REVISED MARCH 2013

www.ti.com

The UVLO pin can also be used to implement various remote enable / disable functions. See the Soft-Start

section for more details.

Reference

The REF pin is the output of a 5V linear regulator that can be used to bias an opto-coupler transistor and

external housekeeping circuits. The regulator output is internally current limited to 20mA (typical).

Current Limit

The LM5039 utilizes two high-speed comparators to implement a current limiting in an overload condition: A

higher threshold (600mV) comparator is used to implement a fast peak cycle-by-cycle current limit to provide

instantaneous protection to the power converter and a lower threshold (500mV) comparator is used to implement

a slower average current limit that balances the half-bridge capacitor divider voltage. During an overload event,

average current limit scheme allows the power converter to act as a constant current source with the duty cycle

maintained such that the average output current is:

(1)

This scheme is often known as “brickwall” current limiting or constant current limiting and its response is same

whether the load is a soft-short or a hard-short. Typically, in an overload condition, the PWM cycle is terminated

by the peak cycle-by-cycle comparator instead of the PWM comparator. This is similar to peak current mode

control, which inherently results in an on-time imbalance between the two phases of a half-bridge topology. Any

such imbalance, for an extended period of time, will cause the voltage at the center point of the capacitor divider

to drift either towards the input voltage or ground. However, in an average current limit scheme, the PWM cycle

is terminated through the PWM comparator, by pulling down the PWM control input. Because of its averaging

nature, the PWM control voltage is essentially held at a constant dc voltage. Therefore, the on-time of successive

PWM cycles are equal, thus maintaining balance of the center-point of the capacitor divider.

Figure 14. Peak Cycle-by-Cycle and Average Current Limit Circuitry

The CS pin is driven by a signal representative of the primary current. During a continuous overload event, the

500mV comparator sources pulses of current into the average current limit pin (ACL). A capacitor connected to

the ACL pin smooths and averages the pulses. When the ACL capacitor is charged to approximately 2V, it starts

pulling down the PWM comparator input via the current mirror shown in Figure 14. As the overload event

persists, the ACL takes control of the duty cycle through the PWM comparator, instead of peak cycle-by-cycle

control. The average current limiting can be disabled by shorting the ACL pin to GND.

12

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