Maximum Duty Cycle =

2

1

LM5039

SNVS621D – FEBRUARY 2010 – REVISED MARCH 2013

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The LM5039 can be synchronized to an external clock by applying a narrow pulse to the RT pin. The external

clock must be at least 10% higher than the free-running oscillator frequency set by the RT resistor. If the external

clock frequency is less than the RT resistor programmed frequency, the LM5039 will ignore the synchronizing

pulses. The synchronization pulse width at the RT pin must range between 15ns to 150ns. The clock signal

should be coupled into the RT pin through a 100 pF capacitor. When the synchronizing pulse transitions low-to-

high (rising edge), the voltage at the RT pin must be driven to exceed 3.2V volts from its nominal 2 VDC level.

During the clock signal’s low time, the voltage at the RT pin will be clamped at 2 VDC by an internal regulator.

The output impedance of the RT regulator is approximately 100

Ω. The RT resistor is always required, whether

the oscillator is free running or externally synchronized.

Gate Driver Outputs (HO & LO)

The LM5039 provides two alternating gate driver outputs, the floating high side gate driver HO and the ground

referenced low side driver LO. Each driver is capable of sourcing 1.25A and sinking 2A peak. The HO and LO

outputs operate in an alternating manner, at one-half the internal oscillator frequency. The LO driver is powered

directly by the VCC regulator. The HO gate driver is powered from a bootstrap capacitor connected between HB

and HS. An external diode connected between VCC (anode pin) and HB (cathode pin) provides the high side

gate driver power by charging the bootstrap capacitor from VCC when the switch node (HS pin) is low. When the

voltage.

The HB and VCC capacitors should be placed close to the pins of the LM5039 to minimize voltage transients due

to parasitic inductances since the peak current sourced to the MOSFET gates can exceed 1.25A. The

recommended value of the HB capacitor is 0.01 µF or greater. A low ESR / ESL capacitor, such as a surface

mount ceramic, should be used to prevent voltage droop during the HO transitions.

The maximum duty cycle for each output is equal to or slightly less than 50% due to a programmed sync rectifier

delay. The programmed sync rectifier delay is determined by the DLY pin resistor. If the COMP pin is open

circuit, the outputs will operate at maximum duty cycle. The maximum duty cycle for each output can be

calculated with the following equation:

where

•

•

T1 is the programmed sync rectifier delay

(4)

programmed delay, the maximum duty cycle at this frequency is calculated to be 50%. Using a programmed sync

rectifier delay of 100 ns, the maximum duty cycle is reduced to 49%. Because there is no fixed deadtime in

LM5039, it is recommended that the delay pin resistor be not less than 10k. Internal delays, which are not

specified, are the only protection against cross conduction if the programmed delay is zero, or very small.

16

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