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KAI-08050 Datasheet(PDF) 26 Page - ON Semiconductor |
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KAI-08050 Datasheet(HTML) 26 Page - ON Semiconductor |
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26 / 31 page ![]() KAI−08050 www.onsemi.com 26 Pixel Timing Detail Figure 22. Pixel Timing Detail P5 P6 P7 VOUT t hv t rv Frame/Electronic Shutter Timing The SUB pin may be optionally clocked to provide electronic shuttering capability as shown below. The resulting photodiode integration time is defined from the falling edge of SUB to the falling edge of V1 (P1 pattern). Figure 23. Frame/Electronic Shutter Timing P1T/B P6 SUB t int t frame t hd t hd t sub Pattern VCCD Clock Edge Alignment Figure 24. VCCD Clock Edge Alignment VVCR 90% 10% tVR tVF tV tVR tVF tV |
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