LB1846MC

No.A2016-3/4

Block Diagram

Truth Tables

IN1

IN2

IN3

IN4

OUT1

OUT2

OUT3

OUT4

Note

L

L

L

L

OFF

OFF

OFF

OFF

Standby

H

L

L

L

H

L

OFF

OFF

H

L

H

L

H

L

H

L

L

L

H

L

OFF

OFF

H

L

L

H

H

L

L

H

H

L

L

H

L

L

L

H

OFF

OFF

L

H

L

H

L

H

L

H

L

L

L

H

OFF

OFF

L

H

H

L

L

H

H

L

L

H

1-2 phase excitation

H

H

-

-

-

-

H

H

The logic output for the first high-level input is

produced. *2

Note: *1 "-" indicates a "don‛t care" input.

*2 If two high levels (H/H) are input to the IN1/IN2 pins with the timing shown in (1) in the figure below, then the IN2 input that arrived later will be

ignored and the IC will function as though an H/L combination is applied to the IN1/IN2 pins. Similarly, the timing shown in (2) results in a L/H

combination on the IN1/IN2 pins.

VCC

OUT1

Stepping

Motor

OUT2

OUT3

OUT4

IN1

IN2

IN3

IN4

GND

L

IN1(IN3)

H

H

L

IN2(IN4)

L

H

(1)

L

IN1(IN3)

L

H

L

IN2(IN4)

H

H

(2)