P2005A, P2005S

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3

Table 3. AC ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Min

Typ

Max

Unit

Input frequency

8

−

32

MHz

Output frequency

1X Option

8

−

32

MHz

4

−

16

Output rise time (measured at 0.8 V to 2.0 V)

0.7

0.9

1.1

nS

Output fall time (measured at 2.0 V to 0.8 V)

0.6

0.8

1.0

nS

Jitter (cycle−to−cycle)

−

−

360

pS

Output duty cycle

45

50

55

%

Table 4. PIN DESCRIPTION

Pin#

Pin Name

Type

Description

1

XIN / CLK

I

Connect to crystal or clock.

2

XOUT

O

Crystal output.

3

DIV2

I

Digital logic input used to select normal output mode or divide−by−two output mode. When this pin

is HIGH, the frequency of the output clock is the same as the input clock frequency. When it is tied

low, the output frequency is half the input clock frequency. This pin has an internal pull−up resistor.

4

VSS

P

Ground to entire chip. Connect to system ground.

5

SR0

I

Digital logic input used to select Spreading Range Refer to Modulation Output and Spreading

Range Selection Table. This pin has an internal pull−up resistor.

6

SSON#

I

Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum func-

tion enabled when LOW, disabled when HIGH. This pin has an internal pull−low resistor.

7

ModOUT

O

Spread spectrum clock output.

8

VDD

P

Power supply for the entire chip (+3.3 V or 5.0 V)

Table 5. OUTPUT FREQUENCY SELECTIONS

Input Frequency

8 MHz

12 MHz

16 MHz

20 MHz

24 MHz

28 MHz

32 MHz

DIV2

4 MHz

6 MHz

8 MHz

10 MHz

12 MHz

14 MHz

16 MHz

Output

Frequency

1 (1X)

8 MHz

12 MHz

16 MHz

20 MHz

24 MHz

28 MHz

32 MHz

Table 6. FREQUENCY DEVIATION SELECTIONS AS A FUNCTION OF INPUT FREQUENCY

P/N

SR0

Input Frequency Range

Modulation Rate (KHz)

8 MHz

12 MHz

16 MHz

20 MHz

24 MHz

28 MHz

32 MHz

P2005A

0

±3.0%

±2.5%

±2.0%

±1.8%

±1.5%

±1.5%

±1.3%

1

±2.5%

±2.0%

±1.8%

±1.5%

±1.3%

±1.3%

±1.0%

P2005S

0

±1.8%

±1.5%

±1.2%

±1.1%

±0.9%

±0.9%

±0.8%

1

±1.5%

±1.2%

±1.1%

±0.9%

±0.8%

±0.8%

±0.6%