CS5132 datasheet(18/20 Pages) ONSEMI

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Application Information: continued

When laying out the CPU buck regulator on a printed cir-

cuit board, the following checklist should be used to ensure

proper operation of the CS5132.

1) Rapid changes in voltage across parasitic capacitors and

abrupt changes in current in parasitic inductors are major

concerns for a good layout.

2) Keep high currents out of sensitive ground connections.

Avoid connecting the IC Gnd between the source of the

lower FET and the input capacitor Gnd.

3) Avoid ground loops as they pick up noise. Use star or

single point grounding.

4) For high power buck regulators on double-sided PCBs a

single ground plane (usually the bottom) is recommended.

5) Even though double sided PCBs are usually sufficient

for a good layout, four-layer PCBs are the optimum

approach to reducing susceptibility to noise. Use the two

internal layers as the power and Gnd planes, the top layer

for the high current connections and component vias, and

the bottom layer for the noise sensitive traces.

6) Keep the inductor switching node small by placing the

output inductor, switching and synchronous FETs close

together.

7) The MOSFET gate traces to the IC must be as short,

straight, and wide as possible. Ideally, the IC has to be

placed right next to the MOSFETs.

8) Use fewer, but larger output capacitors, keep the capaci-

tors clustered, and use multiple layer traces with heavy

copper to keep the parasitic resistance low.

9) Place the switching MOSFET as close to the +5V input

capacitors as possible.

10) Place the output capacitors as close to the load

as possible.

11) Place the VFFB,VOUT filter resistors (510Ω) in series with

the VFFB and VOUT pins as close as possible to the pins.

12) Place the COFF and COMP capacitors as close as possi-

ble to the COFF and COMP pins.

13) Place the current limit filter capacitors between the

VFFB and VOUT pins, as close as possible to the pins.

14) Connect the filter components of the following pins:

VFB, VFFB, VOUT, COFF, and COMP to the LGnd pin with a

single trace, and connect this local LGnd trace to the output

capacitor Gnd.

15) The “Droop” Resistor (embedded PCB trace) has to be

wide enough to carry the full load current.

16) Place the VCC bypass capacitors as close as possible to

the VCC pins and connect them to PGnd.

Layout Guidelines

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