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SM5166AV

NIPPON PRECISION CIRCUITS—5

FUNCTIONAL DESCRIPTION

Operating Frequency Divider

(N-counter) Structure

The

operating

frequency

divider

generates

comparator frequency signal (FV), which is input to

the phase comparator, by dividing the VCO signal

input on pin FIN.

The operating frequency divider is comprised by

dual modulus prescalers, a 5-bit swallow counter and

a 11-bit main counter.

The settings for the prescaler (P and P + 1), swallow

counter (S) and main counter (M) are related to the

comparator frequency divider ratio by:

The counter value ranges are P = 32, P + 1 = 33, S =

0 to 31, and M = 32 to 2047. Therefore, the operating

frequency divider ratio range N is 1056 to 65535.

Reference Frequency Divider

(R-counter) Structure

The

reference

frequency

divider

generates

comparator frequency signal (FR), which is input to

the phase comparator, by dividing the reference

frequency input either from an external signal on

XIN or from a crystal connected between XIN and

XOUT.

The reference frequency divider is comprised by a

ﬁxed divide-by-8 prescaler and an 13-bit reference

counter.

The settings for the prescaler (A = 8) and reference

counter (R) are related to the reference frequency

divider ratio by:

The counter value ranges are A = 8 and B = 5 to

8191. Therefore, the reference frequency divider

ratio range is R = 40 to 65528.

Input Data

The input data should be speciﬁed keeping in mind

the VDD2 supply. The data is input using CLK,

DATA and LE pins into the shift register and latch

which operate from the VDD2 supply. However, the

VDD1 supply level can vary.

The control data input uses a 3-line 17-bit serial

interface comprising the clock (CLK), data input

(DATA) and latch enable (LE). The data is input with

the MSB ﬁrst. The last (17th) bit is used as the latch

select control bit. Data is written to the shift register

on the rising edge of the clock signal. Accordingly,

the data should change state on the falling edge of

the clock signal. Data is transferred from the shift

signal goes HIGH. Accordingly, the latch enable

signal should be held LOW while data is being

written to the shift register.

The clock and data input signals are both ignored

when the latch enable signal goes HIGH. Also, the

CLK, DATA and LE inputs should be tied LOW

when not setting data.

() SP M S

–

()

RAB8B

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