SM5166AV

NIPPON PRECISION CIRCUITS—6

Input Data Format

Shift register timing

Latch select

The last (17th) data bit determines the status of the

shift register data latch.

Swallow counter and main counter frequency divider

Input data example

kHz, then the comparator frequency divider ratio N

is given by:

and the main frequency divider counter count is 314

in figure 3.

Figure 1. Comparator data format

DATA

CLK

LE

12

345

678

9

10 11 12 13 14 15 16 17

MSB

LSB

CONTROL

Table 1. Latch select bit function

Bit 17

Latch

0

Swallow counter and main counter frequency divider

ratio latch select

1

Reference frequency counter divider ratio data and

LD output latch select

Figure 2. Swallow counter and main counter frequency divider data format

DATA

12

345

678

9

10 11 12 13 14 15 16 17

MSB

LSB

22

222

222

22

222

222

10

9

876

543

21

043

210

Main counter

(11-bit : 32 to 2047)

Swallow counter

(5-bit : 0 to 31)

Latch selection bit : Set to "0"

N

f

LO

f

CH

----------

f

VCO

3

×

f

R

3

×

-----------------------

251.3 3

⁄

0.025 3

⁄

--------------------

10052

32

314

4

+

×

==

=

=

=