SM5170AV datasheet(8/10 Pages) NPC

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SM5170AV

NIPPON PRECISION CIRCUITS—8

Input data format example

Reference frequency divider = 144, LD normal operation:

Standby Mode

The SM5170AV enters standby mode when OPR

goes LOW. In this mode, the states and functions

shown in the table occur.

In standby mode, some current ﬂows into VDD1.

Therefore, it is necessary to reduce VDD1 to 0 V to

fully reduce current consumption and reduce power

dissipation. Note that if both the VDD1 and VDD2

supplies are reduced to 0 V, the latch contents will be

erased. In this case, VDD1 only should be reduced to

0 V.

Standby mode is released when VDD1 rises and OPR

goes HIGH.

Phase Comparator Timing Diagram

The DO output circuit polarity is conﬁgured for con-

nection to an external passive ﬁlter.

The signals compared are FV and FR, which are the

internal FIN input frequency divider output signal

and reference frequency divider output signal,

respectively.

Figure 6. Reference counter data and LD output setting example

345

678

MSB

LSB

222

000

010

000

100

Reference Counter (16bit : 5 to 65535)

Control bits

Not used (set to 000)

LDpin Set bit

Test bits (set to 00)

Block

State

DO and DB

Floating (high impedance)

L D

L O W -level output

Phase comparator

Reset

Input FIN

F eedback resistor is cutoff (HIGH level)

Input XIN

F eedback resistor is cutoff (HIGH level)

N counter

Reset

R counter

Reset

Latch data

Stored (while V DD2 is within rating)

Figure 7. Phase comparator timing

SM5170AV Datasheet(PDF) 8 Page - Nippon Precision Circuits Inc

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