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MT8804AP Datasheet(PDF) 6 Page - Mitel Networks Corporation |
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MT8804AP Datasheet(HTML) 6 Page - Mitel Networks Corporation |
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6 / 6 page ![]() MT8804A CMOS 3-8 Figure 6 - Control Memory Timing Diagram Table 1 - Address Decode Truth Table NOTES: 0 - Low Logic Level 1 - High Logic Level X - Don’t Care Condition + - Indicates Connection Between Junctor and Addressed Line • - Indicates No Connection Between Junctor and Addressed Line Memory Reset MR Address Enable AE Address Addressed Line Input Data To Control Memory Junctors Connected To Addressed Line A2 A1 A0 D3 D2 D1 D0 J3 J2 J1 J0 1 X X X X ALL X X X X All Switches "OFF" 0 0 X X X NONE X X X X No Change of State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L0 L0 L0 L0 L0 L0 L0 L0 L0 L0 L0 L0 L0 L0 L0 L0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 • • • • • • • • + + + + + + + + • • • • + + + + • • • • + + + + • • + + • • + + • • + + • • + + • + • + • + • + • + • + • + • + 0 ↓ 0 1 ↓ 1 0 ↓ 0 0 ↓ 0 1 ↓ 1 L1 ↓ L1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 • ↓ + • ↓ + • ↓ + • ↓ + 0 ↓ 0 1 ↓ 1 0 ↓ 0 1 ↓ 1 0 ↓ 0 L2 ↓ L2 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 • ↓ + • ↓ + • ↓ + • ↓ + 0 ↓ 0 1 ↓ 1 0 ↓ 0 1 ↓ 1 1 ↓ 1 L3 ↓ L3 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 • ↓ + • ↓ + • ↓ + • ↓ + 0 ↓ 0 1 ↓ 1 1 ↓ 1 0 ↓ 0 0 ↓ 0 L4 ↓ L4 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 • ↓ + • ↓ + • ↓ + • ↓ + 0 ↓ 0 1 ↓ 1 1 ↓ 1 0 ↓ 0 1 ↓ 1 L5 ↓ L5 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 • ↓ + • ↓ + • ↓ + • ↓ + 0 ↓ 0 1 ↓ 1 1 ↓ 1 1 ↓ 1 0 ↓ 0 L6 ↓ L6 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 • ↓ + • ↓ + • ↓ + • ↓ + 0 ↓ 0 1 ↓ 1 1 ↓ 1 1 ↓ 1 1 ↓ 1 L7 ↓ L7 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 • ↓ + • ↓ + • ↓ + • ↓ + tAEW tAS tDH tPLH/tPHL tPAE tMR tMRR tPLH/tPHL tDS tAH 50% 50% 50% 50% 50% 50% 50% 50% 50% MR AE ADDRESS D0-D3 SWITCH ON OFF |
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