MT8841AS datasheet(4/10 Pages) MITEL

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MT8841

5-14

edge corresponds to the centre of each DATA bit cell

(providing the incoming baud rate matches the DCLK

rate). DCLK is not generated for the stop and start

bits. Consequently, DCLK will clock only valid data

into a peripheral device such as a serial to parallel

shift register or a micro-controller. The CNIC also

outputs an end of word pulse (data ready) at the DR

pin. The data ready signal indicates the reception of

every 10-bit word sent from the Central Office. This

output is typically used to interrupt a micro-controller.

The three outputs together, eliminate the need for a

UART

(Universal

Asynchronous

Receiver

Transmitter) or the high software overhead of

performing the UART function (asynchronous serial

data reception).

Note that the 3-pin interface may also output data

generated by voice since these frequencies are in

the input frequency detection band of the device.

The user may choose to ignore these outputs when

FSK data is not expected, or force the CNIC into its

powerdown mode.

Power Down Mode

For

applications

requiring

reduced

power

consumption, the CNIC can be forced into power

down when it is not needed to receive FSK data.

This is done by pulling the PWDN pin high. In

powerdown mode, the crystal oscillator, op-amp and

internal circuitry are all disabled and the CNIC will

not react to the input signal. DATA and DCLK are at

logic high, and DR and CD are at high impedance or

at logic high when pulled up with resistors.The CNIC

can be awakened for reception of the FSK signal by

pulling the PWDN pin to ground (see Figure 9).

Carrier Detect

The presence of the FSK signal is indicated by a

logic low at the carrier detect (CD) output. This

output has built in hysteresis to prevent toggling

when the received signal is shortly interrupted. Note

that the CD output is also activated by voice since

these

frequencies

are

the

input

frequency

detection band of the device. The user may choose

to ignore this output when FSK data is not expected,

or force the CNIC into its powerdown mode.

Figure 5 - Common Crystal Connection

Crystal Oscillator

The CNIC uses a crystal oscillator as the master

timing source for filters and the FSK demodulator.

The crystal specification is as follows:

Frequency:

3.579545 MHz

Frequency tolerance:

±0.1%(-40°C+85°C)

Resonance mode:Parallel

Load capacitance:

18 pF

Maximum series resistance: 150 ohms

Maximum drive level (mW): 2 mW

e.g. CTS MP036S

A number of MT8841 devices can be connected as

shown in Figure 5 such that only one crystal is

required. The connection between OSC2 and OSC1

can be D.C. coupled as shown, or A.C. coupled

using 30pF capacitors. Alternatively, the OSC1

inputs on all devices can be driven from a CMOS

buffer (dc coupled) with the OSC2 outputs left

unconnected.

VRef and CAP Inputs

VRef is the output of a low impedance voltage source

equal to VDD/2 and is used to bias the input op-amp.

A 0.1µF capacitor is required between CAP and VSS

to suppress noise on VRef.

OSC1

OSC2

OSC1

OSC2

OSC1

OSC2

3.579545 MHz

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