MT8930 datasheet(13/36 Pages) MITEL

13 / 36 page

Preliminary Information

MT8930C

9-47

Figure 13 - Daisy Chaining the SNIC

Figure 14 - NT in Star Configuration

ST-BUS Clock

ST-BUS

Stream

System

Frame Pulse

MT8930C

F0b

F0od

MT8930C

F0b

F0od

MT8930C

F0b

F0od

MT8930C

F0b

F0od

to TE

Active on

Channel 0 - 3

Active on

Channels 4 - 7

Active on

Channels 8 - 11

Active on

Channels 12 - 15

VDD

to TE

STAR

F0b

DSTi

STAR

F0b

DSTi

MT8930C

to TE

System

Frame Pulse

Input

ST-BUS Stream

Output

ST-BUS Stream

STAR

F0b

DSTi

STAR

F0b

DSTi

DSTo

Up to eight SNICs in NT mode with physically

independent S-Busses can be connected in parallel

to realize a star configuration, as shown in Figure 14.

All devices connected into the star will carry the

same input, thus information is sent to all TEs

simultaneously. The 2B+D data received from every

TE is transmitted to all NTs through the STAR pin.

Consequently, all the DSTo streams will carry

identical

2B+D

data

reflecting

what

being

transmitted by the various TEs.

The flow of data in the direction of S-Bus to ST-BUS

is transparent to the SNIC, regardless of the state

machine status. On the other hand, the flow of data

in the direction of ST-BUS to S-Bus becomes

transparent only after the state machine is in the

active state (IS0, IS1=1,1), in case of an NT, or in the

synchronization state (IS0, IS1=1), in case of a TE.

Microprocessor/Control Interface

The parallel port on the SNIC operates as either a

general purpose microprocessor interface or as a

hardwired control port.

In microprocessor control mode (Cmode = 1), the

parallel port is compatible with either Motorola or

Intel multiplexed bus signals and timing.

The

MOTEL

circuit

(MOtorola

and

InTEL

Compatible bus) uses the level of the DS/RD pin

at the rising edge

AS/ALE

select

the

appropriate

bus timing.

If DS/RD is low at the

rising edge of AS/ALE (refer Fig. 26) then Motorola

bus timing is selected.

Conversely,

DS/RD is

high at the rising edge of AS/ALE (refer Figs. 24 &

25), then Intel bus timing is selected. This has the

effect

redefining

the

microprocessor

port

transparently to the user.

In this mode, the user has the option of writing to the

C-channel Control or Diagnostic Register through

the parallel port interface or through the C-channel

on DSTi.

Bit 0 of the Master Control Register

provides this option.

The parallel port on the SNIC allows complete

control of the HDLC transceiver and access to all

data, control and status registers. The internal

registers (defined in Table 2) can be accessed

through the microprocessor port only when the

Cmode pin is held high.

Reading these registers

allows the microprocessor to monitor incoming data

on the S or ST-BUS without interrupting the normal

data flow.

MT8930 Datasheet(PDF) 13 Page - Mitel Networks Corporation

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