MT8930 datasheet(2/36 Pages) MITEL

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MT8930C

Preliminary Information

9-36

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

DIP

PLCC

HALF

HALF Input/Output: this is an input in NT mode and an output in TE mode identifying

which half of the S-interface frame is currently being written/read over the ST-BUS

(HALF = 0 sampled on the falling edge of C4b within the frame pulse low window,

identifies the information to be transmitted/received in the first half of the S-Bus frame

while HALF = 1 identifies the information to be transmitted/received into the second half

of the S-Bus frame). Tying this pin to VSS or VDD in NT mode will allow the device to

free run. This signal can also be accessed from the ST-BUS C-channel.

C4b

4.096 MHz Clock: a 4.096 MHz ST-BUS Data Clock input in NT mode.

In TE mode, a 4.096 MHz output clock phase-locked to the line data signal.

F0b

Frame Pulse: an active low frame pulse input indicating the beginning of active ST-

BUS channel times in NT mode. Frame pulse output in TE mode.

F0od

Delayed Frame Pulse Output: an active low delayed frame pulse output indicating

the end of active ST-BUS channels for this device.

Can be used to daisy chain

to other ST-BUS devices to share an ST-BUS stream.

DSTi

Data ST-BUS Input: a 2048 kbit/s serial PCM/data ST-BUS input with D, C, B1, and B2

channels assigned to the first four timeslots. These channels contain data to be

transmitted on the line and chip control information.

DSTo

Data ST-BUS Output: a 2048 kbit/s serial PCM/data ST-BUS output with D, C, B1 and

B2 channels assigned to the first four timeslots respectively. The remaining timeslots

are placed into high impedance. These channels contain data received from the line

and chip status information.

713

Cmode

Controller Mode Select Input: when high, microprocessor control is selected. When

low the controllerless mode is enabled and the microport pins are redefined as control

inputs and status outputs.

CK/NT

TE Clock/Network Termination Mode Select Input. For TE mode, this pin must be

tied to V

SS or to a 4.096 MHz

clock (a clock is required for standard ISDN TE

applications). For NT mode, this pin must be tied to VDD. Refer to “ST-BUS Interface”

section for further explanation. A pull-up resistor is needed when driven by a TTL

device.

HALF

C4b

F0b

F0od

DSTi

DSTo

Cmode

CK/NT

R/W/WR, AFT/PRI

DS/RD, DinB

AS/ALE, P/SC

CS, DReq

IRQ/NDA, DCack

VSS

VDD

VBias

LTx

LRx

STAR/Rsto

Rsti

AD7, DR

AD6, AR

AD5, M/S

AD4, MCH

AD3, MFR

AD2, SYNC/BA

AD1, IS1

AD0, IS0

28 PIN PDIP/CERDIP

44 PIN PLCC

STAR/Rsto

Rsti

AD7, DR

AD6, AR

AD5, M/S

AD4, MCH

AD3, MFR

F0od

DSTi

DSTo

Cmode

CK/NT

R/W/WR, AFT/PRI

DS/RD, DinB

6 5 4 3 2

444342 41 40

18 19 20 21 22

24 25 26 27 28

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