3-56

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Figure 14 - Timing Information for DPLL #1 in NORMAL Mode

† Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Characteristics

Sym

Min

Max

Units

Test Conditions

1

D

P

L

L

#1

CVb output (1.544 MHz) rise

time

6ns

85 pF Load

2

CVb output (1.544 MHz) fall

time

6

ns

85 pF Load

3

CVb output (1.544 MHz) clock

period

607

648

689

ns

4

CVb output (1.544 MHz) clock

width (HIGH)

318

324

ns

5

CVb output (1.544 MHz) clock

width (LOW)

277

363

ns

6CV delay (HIGH to LOW)

010

ns

7CV delay (LOW to HIGH)

-7

3

ns

Characteristics

Sym

Min

Max

Units

Test Conditions

1

D

P

L

L

#1

C8Kb output (8kHz) delay

(HIGH to HIGH)

0

10

25

ns

85 pF Load

2

C8Kb output (8 kHz) delay

(LOW to LOW )

2

13

34

ns

85 pF Load

3

C8Kb output duty cycle

66

50

%

%

In Divide -1 Mode

In Divide - 2 Mode

4

Inverted clock output delay

(HIGH to LOW )

010

25

ns

5

Inverted clock output delay

(LOW to HIGH)

0

7

18

ns

CVb

CV