MT8952BC datasheet(13/22 Pages) MITEL

13 / 22 page

ISO-CMOS

MT8952B

3-73

FIFO are ﬂagged with two status bits.

The status

bits are found in the FIFO status register and

indicate whether the byte to be read from the FIFO is

the ﬁrst byte of the packet, the middle of the packet,

the last byte of the packet with good FCS or the last

byte of the packet with bad FCS.

This status

indication is valid for the byte to be read from the

receive FIFO.

The incoming data is always written to the FIFO in a

bytewide manner. However, in the event of data sent

not being a multiple of eight bits, the software

associated with the receiver should be able to pick

the data bits from the MSB positions of the last byte

in the received data written to the FIFO.

The

Protocol Controller does not provide any indication

as to how many bits this might be.

Receive FIFO Empty:

When the Receive FIFO is empty, this state is

indicated by the Receive FIFO status bits in the FIFO

Status Register. As with the Tx FIFO status bits (see

Transmit FIFO Full Section), these bits are not

updated for two bit periods after any access of the

Receive FIFO.

If the controlling microprocessor’s

bus cycle is much shorter than a bit period on the

serial port, then the status bits may not be updated

to indicate there is no information left in the Rx FIFO

before the microprocessor has returned to read the

Rx FIFO again. The result is an underﬂow condition

that is only evident by redundant bytes in the

received message.

To avoid a Rx FIFO underﬂow, reading information

from the Rx FIFO

should be approached in two

ways.

The ﬁrst approach is to be used when the

MT8952B indicates (via interrupt) that the Rx FIFO

is 15/19 FULL.

The controlling microprocessor

should then immediately read 14 bytes from the Rx

FIFO.

This will avoid emptying the FIFO.

The

second approach is to be used when an End of

Packet interrupt is signalled by the MT8952B. The

controlling microprocessor should then empty the Rx

FIFO until the Rx Byte Status bits in the FIFO Status

last byte. These bits are “tag“ bits whose state was

determined before the End of Packet condition was

indicated, therefore their state is valid.

Invalid Packets:

If there are less than 24 data bits between the

opening and closing ﬂags, the packet is considered

invalid and the data never enters the receive FIFO.

This is true even with data and the abort sequence,

the total of which is less than 24 bits.

The data

packets that are at least 24 bits but less than 32 bits

long are also invalid, but not ignored.

They are

clocked into the receive FIFO and tagged as having

bad FCS.

Frame Abort:

When a frame abort is received the appropriate bits

in the Interrupt Flag and Status Registers are set.

The last byte of the packet that was aborted is

written to the FIFO with a status of ‘packet byte’

tagged to it. The CPU determines which packet in

the FIFO was aborted, if there is more than one

packet in the FIFO, by the absence of ‘last byte’

status on any of the bytes.

Idle Channel:

While receiving the idle channel, the idle bit in the

general status register remains set.

Go Ahead:

The occurrence of this sequence can be used to

generate an interrupt as described earlier.

The

receive circuitry will not recognize a frame abort

followed by a ﬂag as go ahead.

C-Channel Reception:

The information contained in channel-1 of the

incoming ST-BUS (CDSTi) is shifted into the C-

Channel Status Register during the Internal Timing

Mode.

Transparent Data Transfer:

By setting the IFTF bits in the Control Register to

select the transparent data transfer, the receive

section can be made to disable the protocol

functions like Flag/Abort/GA/Idle detection, zero

deletion, CRC calculation and address comparison.

The received data is shifted in from CDSTi and

written to receive FIFO in bytewide format.

If the

Protocol Controller is in the Internal Timing Mode

and the Timing Control bits are set to 2, 6 or 7 bits/

frame, the respective MSBs of each byte are only to

be read from the data bus.

The transparent data

transfer facility is not available when the Timing

Control bits are set to one bit/frame. The receive

section can be disabled in software immediately

using the RxEN bit in the Control Register.

The operation of the receiver is similar in the

External Timing Mode.

Receive Overﬂow:

Receive overﬂow occurs when the receive section

attempts to load a byte to an already full receive

FIFO.

This status can be used to generate the

interrupt as described earlier.

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