6-34

* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.

Figure 9a - Timing Diagram - 125

µs Frame Period

Receive (D/A) Path (cont’d)

Characteristics

Sym

Min

Typ*

Max

Units

Test Conditions

11

A

N

A

L

O

G

Envelope Delay

210

µs

@ 1004 Hz

12

Envelope Delay 1000-2600 Hz

Variation with

600-3000 Hz

Frequency

400-3200 Hz

90

170

265

µs

µs

µs

Input Signal:

400 - 3200 Hz digital

sinewave at 0 dBm0

13

Gain Relative to

<200 Hz

Gain @ 1004 Hz

200 Hz

(See Figure 11)

300-3000 Hz

3300 Hz

3400 Hz

4000 Hz

≥4600 Hz

-0.5

-0.125

-0.350

-0.80

0.125

0.125

0.125

0.030

-0.100

-14.0

-28.0

dB

dB

dB

dB

dB

dB

dB

0 dBm0 Input Signal

Receive

Filter

Response

14

Crosstalk A/D to D/A

-70

dB

0 dBm0 @ 1.02 kHz

in A/D

15

Power Supply

Rejection

33

35

dB

dB

1.02 kHz

16

Overload Distortion

(See Fig. 15)

Input frequency=1.02 kHz

C2i

INPUT

F1i

INTERNAL

ENABLE

DSTo

OUTPUT

DSTi

INPUT

CA

CSTi

INPUT

LOAD

A-REGISTER

LOAD

B-REGISTER

125

µs

765

432

10

76

543

210

765

432

10

HIGH IMPEDANCE

7

7

76

6

765

432

10

5V

0V

(Mode 3)