6-24

Internally the codec will then perform a decode cycle

on the newly input PCM word.

The sampled and

held analog signal thus decoded will be updated 25

µs from the start of the cycle. After this the analog

input from the filter is sampled for 18 µs, after which

digital conversion takes place during the remaining

82 µs of the sampling cycle.

Since a single clock frequency of 2.048 MHz is

required, all digital data is input and output at this

rate.

DSTo, therefore, assumes a high impedance

state for all but 3.9 µs of the 125 µs frame. Similarly,

DSTi input data is valid for only 3.9 µs.

Digital Control Functions

used to control the function of the filter/codec.

It

operates in three different modes depending on the

logic levels applied to the Control Address input

(CA) and chip enable input (F1i) (see Table 1).

Mode 1

The filter/codec is in normal operation with nominal

transmit and receive gain of 0dB. The SD outputs

are in their active states and the test modes cannot

be entered.

A state of powerdown is forced upon the chip

connected to GNDA and all analog sections have

power removed.

Mode 2

word

CSTi accepts a serial data stream synchronously

with DSTi (i.e., it accepts an eight-bit serial word in a

3.9 µs timeslot, updated every 125 µs, and is

specified

identically

to

DSTi

for

timing

considerations).

This eight-bit control word is

entered

into

Control

Register

A

and

enables

programming of the following functions: transmit and

receive gain, powerdown, loopback.

Register B is

reset to zero and the SD outputs assume their

inactive state. Test modes cannot be entered.

Mode 3

CA=0V (GNDD); CSTi receives an eight-bit control

word

As in Mode 2, the control word enters Register A and

the aforementioned functions are controlled. In this

mode, however, Register B is not reset, thus not

affecting the states of the SD outputs.

In this case the control word is transferred into

Register B. Register A is unaffected. The input and

output of PCM data is inhibited.

The

contents

of

Register

B

controls

the

six

uncommitted outputs SD0-SD5 (four outputs, SD0-

SD3, on MT8960/61/64/65 versions of chip) and also

provide entry into one of the three test modes of the

chip.

Table 1. Digital Control Modes

MODE

CA

CSTi

FUNCTION

1

(Note 1)

GNDD

Normal chip operation.

Powerdown.

Serial

Eight-bit control word into Register A. Register B is reset.

Data

3

(Note 2)

GNDD

Serial

Eight-bit control word into register A. Register B is unaffected.

Data

Serial

Eight-bit control word into register A. Register B is unaffected.

Data

Note 1:

When operating in Mode 1, there should be only one frame pulse (F1i) per 125

µs frame

Note 2: