MT9080 datasheet(8/24 Pages) MITEL

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MT9080 CMOS

2-108

Fig. 7 - Connect Memory Modes Pinout

Data is clocked out on D0o-D15o from memory

locations addressed sequentially by the internal

counter. This counter is incremented every second

clock period and is reset with FP. The frequency of

the clock signal used should be twice the data rate.

A timing diagram showing the relationship between

the data output and the clock signal is presented in

Fig. 8. With a clock rate of 16.384 MHz, the

maximum

number

addresses

that

can

generated in an 8 kHz frame period is 1024.

Fig. 8 - Connect Memory Mode-1 Functional

Timing

Microprocessor access timing is shown in Figures 28

and 29. During a microprocessor read cycle, DS low

indicates to the SMX that the processor is ready to

receive data. The SMX responds by pulling DTA low

when there is valid data present on the bus. The

processor latches the data in and sets DS high. The

SMX completes the bus cycle by disabling the DTA.

DS should be kept low until after DTA is issued by

the SMX.

CS, R/W

and the address lines should

also be asserted for the duration of the access. A

MPU write cycle is similar to the read cycle. Data will

be latched into the device approximately three clock

(CK) cycles after DS goes low.

When the device

has latched the data in, it will pull DTA low. DS can

subsequently be set high.

D0-D15

ODE

MODE

DTA

R/W

A0-A15

D0o-D15o

0/1

Data

Out

1023

Connect Memory Mode-2

Connect Memory Mode-2 is designed specifically for

2048 channel switching applications. Data is clocked

out on D0o-D15o with every rising clock edge from

memory locations addressed sequentially by the

internal counter (see Figure 9).

This counter is

incremented with each clock period and is reset with

FP or when a count of 2047 is reached.

Fig. 9 - Connect Memory Mode-2 Functional

Timing

The clock frequency should be 16.384 MHz for a

connection memory designed to support a 2048

channel switch.

Microprocessor access is similar to Connect Memory

Mode-1.

Counter Mode

This mode is designed for 2048 channel switching

applications. In the counter mode all read and write

addresses are generated sequentially by the internal

11 bit counter.

The 11 bit counter is incremented

with each clock pulse. It will wrap around when it

reaches a count of binary 2047 or when it is reset by

FP. The active input/output pins in this mode are

illustrated in Fig. 10.

Fig. 10 - Counter Mode Pinout

DATA

OUTPUT

2047

D0i-D15i

D0o-D15o

ODE

DTA

R/W

XYZ

All other inputs should

be tied Low

MT9080 Datasheet(PDF) 8 Page - Mitel Networks Corporation

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