MT90823AP datasheet(5/34 Pages) MITEL

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CMOS

MT90823

TCK

Test Clock (5V Tolerant Input): Provides the clock to

the JTAG test logic.

TRST

Test Reset (3.3V Input with internal pull-up):

Asynchronously initializes the JTAG TAP controller by

putting it in the Test-Logic-Reset state. This pin should

be pulsed low on power-up, or held low, to ensure that

the MT90823 is in the normal functional mode.

Internal Connection (3.3V Input with internal

pull-down): Connect to VSS for normal operation. This

pin must be low for the MT90823 to function normally

and to comply with IEEE 1149 (JTAG) boundary scan

requirements.

RESET

Device Reset (5V Tolerant Input): This input (active

LOW) puts the MT90823 in its reset state to clear the

device internal counters, registers and bring STo0 - 15

and microport data outputs to a high impedance state.

The time constant for a power up reset circuit must be a

minimum of ﬁve times the rise time of the power supply.

In normal operation, the RESET pin must be held low

for a minimum of 100nsec to reset the device.

WFPS

Wide Frame Pulse Select (5V Tolerant Input): When

1, enables the wide frame pulse (WFP) Frame

Alignment interface. When 0, the device operates in

ST-BUS/GCI mode.

41 -

14-21

11 -

N6,M7,N7,N8,

M8,N9,M9,N10

A0 - A7

Address 0 - 7 (5V Tolerant Input): When

non-multiplexed CPU bus operation is selected, these

lines provide the A0 - A7 address lines to the internal

memories.

N11

DS/RD

Data Strobe / Read (5V Tolerant Input): For Motorola

multiplexed bus operation, this input is DS. This active

high DS input works in conjunction with CS to enable

the read and write operations.

For Motorola non-multiplexed CPU bus operation, this

input is DS. This active low input works in conjunction

with CS to enable the read and write operations.

For multiplexed bus operation, this input is RD. This

active low input sets the data bus lines (AD0-AD7,

D8-D15) as outputs.

M10

R/W / WR Read/Write / Write (5V Tolerant Input): In the cases

of Motorola non-multiplexed and multiplexed bus

operations, this input is R/W. This input controls the

direction of the data bus lines (AD0 - AD7, D8-D15)

during a microprocessor access.

For multiplexed bus operation, this input is WR. This

active low input is used with RD to control the data bus

(AD0 - 7) lines as inputs.

Pin Description (continued)

Pin #

Name

Description

PLCC

100

MQFP

100

LQFP

120

BGA

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