Preliminary Information

MT9123

8-57

Figure 5 - ST-BUS 8 Bit Companded PCM I/O on Timeslots 0 & 1 (Mode 1)

Figure 6 - ST-BUS 8 Bit Companded PCM I/O on Timeslots 2 & 3 (Mode 2)

C4i

F0i

Sin

Rout

Rin

Sout

F0od

76 5 4

76 5 4 3 21 0

3 21 0

76 5 4

76 5 4 3 21 0

3 21 0

76 5 4

76 5 4 3 21 0

3 21 0

76 5 4

76 5 4 3 21 0

3 21 0

outputs=High impedance

inputs = don’t care

ECA

ECB

In ST-BUS Mode 1, both echo canceller I/O channels are assigned to ST-BUS timeslots 0 and 1. Note that the user

could configure PORT1 and PORT2 into different ST-BUS modes. The pin F0od is always delayed 4 time slots to permit

a more flexible interleave of ST-BUS modes.

PORT1

PORT2

01

2

3

4

ECA

ECB

C4i

F0i

Sin

Rout

Rin

Sout

F0od

76 5 4

76 5 4 3 21 0

3 21 0

76 5 4

76 5 4 3 21 0

3 21 0

76 5 4

76 5 4 3 21 0

3 21 0

76 5 4

76 5 4 3 21 0

3 21 0

ECA

ECB

In ST-BUS Mode 2, both echo canceller I/O channels are assigned to ST-BUS timeslots 2 and 3. Note that the user

could configure PORT1 and PORT2 into different ST-BUS modes. The pin F0od is always delayed 4 time slots to permit

a more flexible interleave of ST-BUS modes.

ECA

ECB

PORT1

PORT2

01

2

3

4

outputs=High impedance

inputs = don’t care