PDSP16318/16318A

4

GC pin

77

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

5

Function

D7

D8

D9

D10

GND

VCC

D11

D12

D13

D14

D15

C15

C14

C13

C12

VCC

GND

C11

C10

C9

C8

GC pin

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

Function

C7

C6

C5

C4

C3

C2

C1

C0

OED

OEC

S2

S1

S0

MS

ASI1

ASI0

DEL

CLR

ASR1

ASR0

A0

GC pin

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

Function

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

CEA

B15

B14

B13

B12

B11

GC pin

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

Function

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

CLK

CEB

OVR

D0

D1

D2

D3

D4

D5

D6

Device Pinout for ceramic QFP (GC100)

ASX1

0

0

1

1

ASR or ASI

ASX0

0

1

0

1

A + B

A

A - B

B - A

ALU Function

MS

0

1

Real and Imag' Mux Control

B port input/Del mux output

C accumulator/D accumualtor

DEL

0

1

Delay Mux Control

A port input

Delayed A port input

S2

0

0

0

0

1

1

1

1

S1

0

0

1

1

0

0

1

1

S0

0

1

0

1

0

1

0

1

19

15

18

14

15

17

13

14

15

16

12

13

14

15

15

11

12

13

14

15

14

10

11

12

13

14

15

13

9

10

11

12

13

14

15

12

8

9

10

11

12

13

14

15

11

7

8

9

10

11

12

13

14

10

6

7

8

9

10

11

12

13

9

5

6

7

8

9

10

11

12

8

4

5

6

7

8

9

10

11

7

3

4

5

6

7

8

9

10

6

2

3

4

5

6

7

8

9

5

1

2

3

4

5

6

7

8

4

0

1

2

3

4

5

6

7

3

0

1

2

3

4

5

6

2

0

1

2

3

4

5

1

0

1

2

3

4

0

0

1

2

3

S2:0

Adder result

NOTE

This table shows the portion of the adder result passed to the D15:0 and C15:0 outputs. Where fewer than 16 adder bits are selected

the output data is padded with zeros.