SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(BUF)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

P

S

S

P

TMP435

www.ti.com

SBOS495A – MARCH 2010 – REVISED APRIL 2010

TIMING DIAGRAMS

Data Transfer: The number of data bytes transferred

between a START and a STOP condition is not

The TMP435 is two-wire and SMBus-compatible.

limited and is determined by the master device. The

Figure

15

to

Figure

19

describe

the

various

receiver acknowledges the transfer of data.

operations on the TMP435. Bus definitions are given

below. Parameters for Figure 15 are defined in

Acknowledge:

Each

receiving

device,

when

Table 15.

addressed, is obliged to generate an Acknowledge

bit. A device that acknowledges must pull down the

Bus Idle: Both SDA and SCL lines remain high.

SDA line during the Acknowledge clock pulse in such

a way that the SDA line is stable low during the high

Start Data Transfer: A change in the state of the

period of the Acknowledge clock pulse. Setup and

SDA line, from high to low, while the SCL line is high,

hold times must be taken into account. On a master

defines a START condition. Each data transfer is

receive, data transfer termination can be signaled by

initiated with a START condition.

the master generating a Not-Acknowledge on the last

Stop Data Transfer: A change in the state of the

byte that has been transmitted by the slave.

SDA line from low to high while the SCL line is high

defines

a

STOP

condition.

Each

data

transfer

terminates with a STOP or a repeated START

condition.

Figure 15. Two-Wire Timing Diagram

Table 15. Timing Diagram Definitions for Figure 15

FAST MODE

HIGH-SPEED MODE

PARAMETER

MIN

MAX

MIN

MAX

UNITS

SCL Operating Frequency

0.001

0.4

0.001

3.4

MHZ

Bus Free Time Between STOP

ns

600

160

and START Condition

Hold time after repeated START

condition. After this period, the

100

100

ns

first clock is generated.

Repeated START Condition Setup

100

100

ns

Time

STOP Condition Setup Time

100

100

ns

Data Hold Time

ns

Data Setup Time

100

10

ns

SCL Clock LOW Period

1300

160

ns

SCL Clock HIGH Period

600

60

ns

Clock/Data Fall Time

300

160

ns

Clock/Data Rise Time

300

160

ns

for SCLK

≤ 100kHz

1000

ns

(1)

For cases with fall time of SCL less than 20ns and/or the rise time or fall time of SDA less than 20ns, the hold time should be greater

than 20ns.

(2)

For cases with fall time of SCL less than 10ns and/or the rise or fall time of SDA less than 10ns, the hold time should be greater than

10ns.

Copyright © 2010, Texas Instruments Incorporated

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