Z86131 datasheet(21/50 Pages) ZILOG

21 / 50 page

Z86129/130/131

P R E L I M I N A R Y

NTSC Line 21 Decoder

DS96TEL0200

The master's sequence for reading two

data bytes (total

of three bytes including SSB) from the Z86129/130/131 is

given as:

Start-Slave Address Read/Slave ACK-SS Byte/Master

ACK-Byte (slave)/Master ACK-Byte (slave)/Master NACK-

Stop

Clock and Data Transitions. The SCK and SDA bus lines

are normally pulled High with a resistor. Data on the SDA

bus may only change during SCK Low time periods. Data

changes during SCK High periods will indicate a start or

stop condition as defined in Table 7.

Start Condition. A High-to-Low transition of SDA with

SCK High is a start condition which must precede any

other command.

Stop Condition. A Low-to-High transition of SDA with

SCK High is a stop condition which terminates all

communications.

Acknowledge. All address and data words are serially

transmitted to and from the Z86129/130/131 in eight bit

words. A ninth bit time is used for the acknowledge. The

acknowledging device does so by pulling the SDA bus Low

during the ninth bit. A Not Acknowledge (NACK) is given

by SDA=High during the ninth clock time.

Figure 10. I2C Bus READ (Command)

STRT

STOP

SLAVE

SERIAL

ADDR

STATUS

(READ=29h)

(SSB)

NACK

STRT

STOP

SLAVE

SERIAL

ADDR

STATUS

(READ=29h)

(SSB)

READ

DATA1

NACK

STRT

STOP

SLAVE

SERIAL

ADDR

STATUS

(READ=29h)

(SSB)

READ

DATA1

READ

DATA2

NACK

I2C-One Byte Write (Status Only)

I2C-Two Byte Read (Status & Data1)

I2C-Three Byte Read (Status, Data1, & Data2)

Note: In all I2C Read operations deﬁned herein, the last byte read

from the Z86129/130/131 must be acknowledged by the master

with a NACK (Not ACKnowledge).

Figure 11. I2C Serial Timing

SDA (IN)

SCK

SDA (OUT)

SU.STA

HD.STA

HightLow

HD.DAT

SU.DAT

SU.STO

BUF

Table 7. I2C Serial Timing Min/max

Symbol

Parameter

Min

Max

Units

SCK

Clock Frequency

100

kHz

LOW

Clock Pulse Width Low

4.7

–

µs

High

Clock Pulse Width High

4.0

–

µs

SDA and SCL Rise Time

–

1.0

µs

SDA and SCL Fall Time

–

300

Clock Low to Data Out Valid

0.1

3.5

µs

BUF

Bus Free Time

4.7

–

µs

HD.STA

Start Hold Time

4.0

–

µs

SU.STA

Start Set-up Time

4.7

–

µs

HD.DAT

Data In Hold Time

–

µs

SU.DAT

Data In Set-up Time

250

–

SU.STO

Stop Set-up Time

4.7

–

µs

Data Out Hold Time

100

–

Input Filter Time Constant

100

Z86131 Datasheet(PDF) 21 Page - Zilog, Inc.

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