Z86C8316VSC datasheet(16/46 Pages) ZILOG

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Z86C83/C84

® MCU Microcontrollers

DS96DZ80203

PIN FUNCTIONS

Application Precaution

The production test-mode environment may be enabled

accidentally during normal operation if

excessive noise

surges above V

cc occur on the /RESET pin.

Recommendations for dampening voltage surges in both

test and OTP mode include the following:

Using a clamping diode to /RESET

Adding a capacitor to the affected pin

XTAL1.

Crystal 1 (time-based input). This pin connects a

parallel-resonant crystal, ceramic resonator, LC network

or an external single-phase clock to the on-chip oscillator

input.

XTAL2.

Crystal 2 (time-based output). This pin connects a

parallel-resonant crystal, ceramic resonator, LC network to

the on-chip oscillator output.

Port 0 P00-P06.

(P03-P06

not

available

the

Z86C84). Port 0 is a 7-bit, bidirectional, CMOS-compatible

I/O

port.

These

seven

I/O

lines

can

nibble

programmable as P00-P03 input/output and P04-P06

input/output, separately (Figure 10). All input buffers are

Schmitt-triggered and output drivers are push-pull. There

is a ROM mask option to enable 100K (

±40%) pull-up

resistors to Port 0, P00 to P02.

Port 0 Auto Latch.

(Auto Latch Mask Option available

only on P00-P02. P03-P06 has the Auto Latches

permanently enabled.) The Auto Latch provides valid

CMOS Levels when P00-P06 (P00-P02 on C84) are

selected as inputs and not externally driven. It is

impossible to determine if a non-driven input is 1 or 0,

however; the Auto Latch will sense the input condition and

drive a valid CMOS level, thereby eliminating a floating

mode that could cause excessive current. (Auto Latch is a

ROM mask option for the Z86C83, Z86C84).

Port 2 (P27-P20) Port 2 is an 8-bit, bi-directional, CMOS-

compatible I/O port and an 8-channel muxed input to the

8-bit ADC. When configured as a digital input, by

programming the Port2 Mode register, the Port 2 register

can be evaluated to read digital data applied to Port 2, or

the ADC result register can be read to evaluate the analog

signals applied to Port 2 after configuring the ADC Control

Registers. The direction of each of the eight Port 2 I/O lines

can be configured individually (Figure 11).

In addition, all four versions of the device provide the

capability of connecting 10K (

±20%) pull-up resistors to

each of the Port 2 I/O lines individually. The pull-ups are

connected when activated through software control of

P2RES register (Figure 67) when the corresponding Port

2 pin is configured to be an input. The pull-up resistor of a

Port 2 I/O line is automatically disabled when the

corresponding I/O is an output, regardless of the state of

the corresponding P2RES bit value.

Note: The Z86C83/C84 Emulator does not emulate the

P2RES Register. Selection of the pull-ups are done via

jumper settings on the emulator.

Z86C8316VSC Datasheet(PDF) 16 Page - Zilog, Inc.

Z86C8316VSC Datasheet(HTML) 16 Page - Zilog, Inc.

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