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Z86743 Datasheet(PDF) 7 Page - Zilog, Inc.

Part # Z86743
Description  CMOS Z8 OTP Microcontrollers
PDF  10 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z86743 Datasheet(HTML) 7 Page - Zilog, Inc.

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Z86E33/733/E34/E43/743/E44
Zilog
CMOS Z8® OTP Microcontrollers
CP97DZ83300
P R E L I M I N A R Y
7
1
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; functional operation of the
device at any condition above those indicated in the oper-
ational sections of these specifications is not implied. Ex-
posure to absolute maximum rating conditions for an ex-
tended period may affect device reliability.
Total power dissipation should not exceed 1.2 W for the
package. Power dissipation is calculated as follows:
Total Power Dissipation = VDD x [ IDD – (sum of IOH) ]
+ sum of [ (VDD – VOH) x IOH ]
+ sum of (V0L x I0L)
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin
(Test Load).
Parameter
Min
Max
Units
Ambient Temperature under Bias
–40
+105
C
Storage Temperature
–65
+150
C
Voltage on any Pin with Respect to VSS [Note 1]
–0.6
+7
V
Voltage on VDD Pin with Respect to VSS
–0.3
+7
V
Voltage on XTAL1 and /RESET Pins with Respect to VSS [Note 2]
–0.6
V DD+1
V
Total Power Dissipation
1.21
W
Maximum Allowable Current out of VSS
220
mA
Maximum Allowable Current into VDD
180
mA
Maximum Allowable Current into an Input Pin [Note 3]
–600
+600
µA
Maximum Allowable Current into an Open-Drain Pin [Note 4]
–600
+600
µA
Maximum Allowable Output Current Sinked by Any I/O Pin
25
mA
Maximum Allowable Output Current Sourced by Any I/O Pin
25
mA
Notes:
1. This applies to all pins except XTAL pins and where otherwise noted.
2. There is no input protection diode from pin to VDD.
3.
This excludes XTAL pins.
4.
Device pin is not at an output Low state.
Figure 7. Test Load Diagram
150 pF
From Output
Under Test



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