5

PRELIMINARY

Z89303/05/07

CPS DC-4222-03

V1, V2, V3 ANALOG OUTPUT

Specifications V

V

Condition

Limit

Output Voltage

Bit = 11

4.55 V +/– 0.25 V

Bit = 10

3.205V +/– 0.2 V

Bit = 01

1.95 V +/– 0.15 V

Bit = 00

0.65 V +/– 0.1 V

Settling Time

70% of DC Level, 10pf Load

< 50 nsec

V1, V2, V3 ANALOG OUTPUT

Specifications V

V

Condition

Limit

Output Voltage

Bit = 11

3.90 V +/– 0.25 V

Bit = 10

2.90 V +/– 0.2 V

Bit = 01

1.90 V +/– 0.15 V

Bit = 00

0.1 V +/– 0.1 V

Settling Time

70% of DC Level, 10pf Load

< 50 nsec

32K Oscillator Recommended Circuit

Notes:

c) PWM[8,7] is not available on the 40-pin DIP version.

d) Port0[F:A] is not available on the 40-pin DIP version.

e) Port19 is not available on the 40-pin DIP version.

f)

SCL I/O pin is shared with Port0 or Port11.

g) SCD I/O pin is shared with Port02 or Port12.

h) Half Blank output is a function shared with Port0F.

Half Blank output is not available on the 40-pin DIP version.

i)

Digital RGB outputs and the internal SCLK are shared with Port1[5:0].

k)

Internal processor SCLK is shared with Port16.

Z893XX