LMP92064

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SNOSCX0A – JUNE 2013 – REVISED DECEMBER 2014

7.5 Register Maps

1. If written to, Reserved bits must be written to 0, unless otherwise indicated.

2. Read back value of Reserved bits and registers is unspecified and should be discarded.

3. Recommended values must be programmed and forbidden values must not be programmed where they are

indicated in order to avoid unexpected results.

4. If written to, registers indicated as Reserved must have the indicated default value as shown in the register

map. Any other value can cause unexpected results.

Table 3. Register Map

REGISTER NAME

REGISTER DESCRIPTION

ADDRESS

ACCESS

DEFAULT

CONFIG_A

Interface Configuration A

0x0000

R/W

0x18

CONFIG_B

Interface Configuration B

0x0001

R/W

0x00

Reserved

Reserved

0x0002

R/W

0x00

CHIP_TYPE

Chip Type

0x0003

RO

0x07

0x0004

0x00

CHIP_ID

Chip ID

RO

0x0005

0x04

CHIP_REV

Chip Revision

0x0006

RO

0x01

0x000C

0x51

MFR_ID

Manufacturer ID

RO

0x000D

0x04

REG_UPDATE

Register Update

0x000F

R/W

0x00

CONFIG_REG

LMP92064 Specific Configuration Register

0x0100

R/W

0x00

STATUS

Status Register

0x0103

RO

N/A

0x0200

DATA_VOUT

Voltage Channel Output Data

RO

N/A

0x0201

0x0202

DATA_COUT

Current Channel Output Data

RO

N/A

0x0203

Table 4. CONFIG_A: Interface Configuration A

ADDR

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0x0000

RESET

DDIR

ADDRDIR

SDDIR

[7]

Soft reset (self-clearing)

R/W

0: Normal (default)

1: Reset

[6]

DDIR

Data direction

RO

0: Data is transmitted MSB first (default)

[5]

Multiple-read auto-address direction

RO

0: Address auto-decrements (default)

[4]

SSDIR

Serial data direction

RO

1: Unidirectional; SDI is used for write and SDO is used for read (default)

[3:0]

Bits [3:0] should always mirror [7:4] as follows:

R/W

[3] = [4]

[2] = [5]

[1] = [6]

[0] = [7]

(1)

Contents of register 0x0000 and 0x0001 and SPI state machine are unaffected

(2)

Address 0x0000 will wrap to 0x7FFF

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