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AS8202B

Datasheet - Detailed Descr i p ti on

Asynchronous READYB permits the shortest possible bus cycle but eventually requires signal synchronization in the application. Connect

USE_RAM_CLK to VSS to enable this mode of operation.

Synchronous READYB uses an external clock (usually the host processor’s bus clock) for synchronization of the signal, eliminating external

synchronization logic. Connect USE_RAM_CLK to VDD and RAM_CLK_TESTSE to the host processor's bus clock to enable this mode of

operation.

Note: Due to possible metastability occurrence, it is not recommended to be used in safety critical systems.

Table 5. Asynchronous DPRAM Interface

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Tc

Controller Cycle Time

25

ns

1a

Input Valid to CEB, WEB (Setup Time)

A[11:0]

5ns

2a

D[15:0]

1b

CEB, WEB to Input Invalid (Hold Time)

A[11:0]

3

ns

2b

D[15:0]

4

3

Input Rising to CEB, WEB Falling

CEB, WEB, OEB

5

(see note 1)

ns

4

CEB, WEB Rising to Input Falling

CEB, WEB, OEB

5

(see note 1,2)

ns

5

Write Access Time (CEB, WEB to

READYB)

Min = 1 Tc, Max = 4 Tc

25

100

ns

6

CEB, WEB de-asserted to READYB

de-asserted

9.4

ns

7a

Input Valid to CEB, OEB (Setup Time)

A[11:0]

5

ns

7b

CEB, OEB to Input Invalid (Hold Time)

A[11:0]

2

ns

8

Input Rising to CEB, OEB Falling

CEB, WEB, OEB

5

(see note 1)

ns

9

CEB, OEB Rising to Input Falling

CEB, WEB, OEB

5

(see note 1)

ns

10

Read Access Time (CEB, OEB to

READYB)

Min = 1.5 Tc, Max = 8 Tc

37.5

200

ns

11a

CEB, OEB asserted to signal asserted

D[15:0]

4.0

8.4

ns

11b

CEB, OEB de-asserted to signal de-

asserted

D[15:0]

3.8

8

ns

11c

READYB

8.8

12

READYB, D skew

±2

ns

13

RAM_CLK_TESTSE Rising to

READYB Falling

USE_RAM_CLK=1

3.7

13.5

ns

14

RAM_CLK_TESTSE Rising to

READYB Rising

USE_RAM_CLK=1

3

9.7

ns

15

RAM_CLK_TESTSE Rising to

READYB Deactivated 1->Z

USE_RAM_CLK

=1

Ready

delay=00

3.6

12.9

ns

Ready

delay=01

4.5

15.4

Ready

delay=10

5.4

18.8

Ready

delay=11

6.4

22.2

16

Read to Read Access Inactivity Time

(CEB, OEB low to CEB, OEB low)

Min = 1.5 Tc

37.5

(see note 1)

ns