SL13A-ASWB datasheet(33/49 Pages) AMSCO

33 / 49 page

ams Datasheet: 2014-May-06 [v1-01]

SL13A – 33

C o mmands

The Address field holds the EEPROM address. Data field contains

the EEPROM data or Test vector.

The SPI communication is always organized into frames of 6

bytes, any other number of bytes will result in a communication

error. The communication has to end with a clock pulse - the

'execute' pulse. The whole number of clock pulses in a

communication frame is 49.

The only operation that requires more bytes is the EEPROM read

operation. After the 49th clock pulse, another 33 clock pulses

have to be generated, with a delay of at least 30

μs after the

'execute' pulse. The data is shifted out with the last 32 clock

pulses.

The SPI supply will send an IRQ on the D_OUT pin after the

command is executed. In the SPI Write command, the D_OUT

signal will go high after the EEPROM write operation is fully

completed. This typically takes 12ms. In the SPI Read command,

the D_OUT signal will go high after the data is ready to be read.

In order to read the data, the master has to send 1 additional

clock pulse – the ACK pulse – before he starts to read the 32 bits

of data. In a Read command, the full operation takes 82 clock

pulses (48 for command + 1 Execute + 1 ACK + 32 data read).

The SPI interface is referenced to the VBAT supply. If the chip is

used in fully passive mode with external circuitry, the SPI

interface is referenced to the VEXT supply.

Figure 21:

SPI Write Operation

SL13A-ASWB Datasheet(PDF) 33 Page - ams AG