TAS5731MPHPR datasheet(66/81 Pages) TI1

66 / 81 page

TAS5731M

SLOS838C – JULY 2013 – REVISED AUGUST 2015

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10.2.2.1 Design Requirements

SPACE

Table 26. Design Requirements

PARAMETER

EXAMPLE

Low Power Supply

3.3 V

High Power Supply

8 V to 24 V

I2S Compliant Master

Host Processor

I2C Compliant Master

GPIO Control

Output Filters

Inductor-Capacitor Low Pass Filter

Speaker

Ω minimum

10.2.2.2 Detailed Design Procedure

Refer to Detailed Design Procedure for information.

10.2.2.3 Application Curves

SPACE

Table 27. Relevant Performance Curves

CURVE TITLE

FIGURE

Output Power vs Supply Voltage (PBTL Mode)

Figure 32

With 2

ω Load on Typical 2 Layer PCB, Device May Be Thermally Limited Above 20 V

Total Harmonic Distortion + Noise vs Output Power (PBTL Mode)

Figure 33

Total Harmonic Distortion + Noise vs Output Power (PBTL Mode)

Figure 34

Total Harmonic Distortion + Noise vs Output Power (PBTL Mode)

Figure 35

Total Harmonic Distortion vs Frequency (PBTL Mode)

Figure 36

Total Harmonic Distortion vs Frequency (PBTL Mode)

Figure 37

Total Harmonic Distortion vs Frequency (PBTL Mode)

Figure 38

Efficiency vs Output Power (PBTL Mode)

Figure 39

Efficiency vs Output Power (PBTL Mode)

Figure 40

Power vs Supply Voltage (PBTL Mode)

Figure 41

Idle Channel Noise vs Supply Voltage (PBTL Mode)

Figure 42

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