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TMG39921 Datasheet(PDF) 49 Page - ams AG |
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TMG39921 Datasheet(HTML) 49 Page - ams AG |
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49 / 95 page ![]() ams Datasheet Page 49 [v1-04] 2014-Oct-24 Document Feedback TMG3992 − Register Description Wait Time Register (WTIME 0x83) The WTIME controls the amount of time in a low power mode between Proximity and/or ALS cycles. It is set 2.78ms increments unless the WLONG bit is asserted in which case the wait times are 12× longer. WTIME is programmed as a 2’s complement number. Upon power up, the wait time register is set to 0xFF. Figure 48: Wait Time Register Note(s) and/or Footnote(s): 1. The wait time register should be configured before AEN and/or PEN is asserted. 2. During any Proximity and/or ALS cycle, the wait state, depicted in the functional block diagram, is entered. For example, Proximity only, Proximity and ALS, or ALS only cycles always enter the WAIT state and are separated by the time defined by WTIME. 765 432 1 0 WTIME Field Bits Description WTIME 7:0 REGISTER VALUE WAIT TIME TIME (WLONG=0) TIME (WLONG=1) 0xFF 1 2.78 ms 0.03 sec 0xAB 85 236 ms 2.84 sec …. …. …. 0x00 256 712 ms 8.54 sec 256 TIME 2.78ms ------------------ – = |
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