SI53313 datasheet(13/33 Pages) SILABS

13 / 33 page

Si53313

Rev. 1.0

2.2. Input Bias Resistors

Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected.

The non-inverting input is biased with a 18.75 k

 pulldown to GND and a 75 k pullup to VDD. The inverting input

is biased with a 75 k

 pullup to VDD.

Figure 6. Input Bias Resistors

2.3. Voltage Reference (VREF)

The VREF pin can be used to bias the input receiver, as shown in Figure 7 when a single-ended input clock (such

as LVCMOS) is used. Note that VREF = VDD/2 and should be compatible with the VCM rating of the single-ended

input clock driving the CLK0 or CLK1 inputs. To optimize jitter and duty cycle performance, use the circuit in

Figure 4. VREF pin should be left floating when differential clocks are used.

Figure 7. Using Voltage Reference with Single-Ended Input Clock

RPU

CLK0 or

CLK1

RPU

RPU = 75 kohm

RPD = 18.75 kohm

RPD

–

VDD

Si53313

CLKx

VREF

100 nF

VDDO = 3.3 V, 2.5 V

CMOS Driver

SI53313 Datasheet(PDF) 13 Page - Silicon Laboratories