Rev 2.6, August 1, 2010

Page 4 of 8

SL16010DC

Frequency Range

FR-2

REFCLK, Pin 9

-

27.000

-

MHz

Frequency Range

FR-3

SSCLK, Pin 5

-

100.000

-

MHz

Frequency Accuracy

FACC1

REFCLK, Pin 9

-30

+/-0

30

ppm

Frequency Accuracy

FACC2

SSCLK, Pin 5, SSEL0/1=0

-30

+/-0

30

ppm

Rise and Fall Time

TR/F-1

REFCLK, Pin 9, CL=5pF, measured

from 20% to 80% of VDD

-

1.0

1.5

ns

Rise and Fall Time

TR/F-2

REFCLK, Pin 9, CL=15pF, measured

from 20% to 80% of VDD

-

1.5

2.0

ns

Rise and Fall Time

TR/F-3

SSCLK, Pin 5, CL=5pF, measured

from 20% to 80% of VDD

-

0.75

1.0

ns

Rise and Fall Time

TR/F-4

SSCLK, Pin 5, CL=15pF, measured

from 20% to 80% of VDD

-

1.5

1.75

ns

Output Duty Cycle

DC

SSCLK and REFCLK, Pins 5 and 9,

measured at VDD/2, CL=15pF

45

50

55

%

Cycle-to-Cycle Jitter

CCJ

SSCLK/REFCLK, Pins 5 and 9

-

125

200

ps

Long Term Jitter

LTJ

REFCLK, Pins 9, 10,000 cycles

-

130

300

ps

Power-up Time

(VDD)

tPU1

Time from 0.9VDD to valid frequency

at output Pins 5 and 9

-

2.0

5.0

ms

Spread Percent

Change Settling Time

tSS%

Time from SSEL0/1 change to stable

SSCLK with spread %

-

-

1.0

ms

Modulation Frequency

MF

SSCLK, 100MHz nominal, Pin 5

31

32

33

kHz

Modulation Type and

Slew Rate

FMTSR

SSCLK, Pin 5, Triangular Modulation

Profile

-

-

0.125

%/μs

Table 5. SSEL1 and SSEL0 versus Spread % Selection at SSCLK

SSEL1 (Pin 3)

SSEL0 (Pin 7)

Spread Percent (%)

SSCLK (Pin 5)

Low (VSS)

Low (VSS)

Spread Off (No Spread)

Low (VSS)

Middle (VDD/2)

-0.50%

Low (VSS)

High (VDD)

-2.5%

Middle (VDD/2)

Low (VSS)

-0.25%

Middle (VDD/2)

Middle (VDD/2)

-0.75%

Middle (VDD/2)

High (VDD)

-1.0%

High (VDD)

Low (VSS)

-1.5%

High (VDD)

Middle (VDD/2)

-2.0%

High (VDD)

High (VDD)

-3.0%

Note: Middle (VDD/2) state requires 5k

Ω/5kΩ external resistors as shown in Figure 3, page 5.