MEC1322 datasheet(337/456 Pages) MICROCHIP

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DS00001719D-page 337

MEC1322

In the following register definitions, a “PWM period” is defined by time the PWM counter goes from 000h to its maximum

value (FFh in 8-bit mode, FEh in 7-bit mode and FCh in 6-bit mode, as defined by the PSCALE field in register

LED_CFG). The end of a PWM period occurs when the PWM counter wraps from its maximum value to 0.

The registers in this block can be written 32-bits, 16-bits or 8-bits at a time. Writes to LED Configuration Register take

effect immediately. Writes to LED Limits Register are held in a holding register and only take effect only at the end of a

PWM period. The update takes place at the end of every period, even if only one byte of the register was updated. This

means that in blink/PWM mode, software can change the duty cycle with a single 8-bit write to the MIN field in the

LED_LIMIT register. Writes to LED Delay Register, LED Update Stepsize Register and LED Update Interval Register

also go initially into a holding register. The holding registers are copied to the operating registers at the end of a PWM

period only if the Enable Update bit in the LED Configuration Register is set to 1. If LED_CFG is 0, data in the holding

registers is retained but not copied to the operating registers when the PWM period expires. To change an LED breath-

ing configuration, software should write these three registers with the desired values and then set LED_CFG to 1. This

mechanism ensures that all parameters affecting LED breathing will be updated consistently, even if the registers are

only written 8 bits at a time.

28.10.1

LED CONFIGURATION REGISTER

TABLE 28-16: EC-ONLY REGISTER SUMMARY

Offset

00h

LED Configuration Register

04h

LED Limits Register

08h

LED Delay Register

0Ch

LED Update Stepsize Register

10h

LED Update Interval Register

Offset

00h

Bits

Description

Type

Default

Reset

Event

31:16 Reserved

16 SYMMETRY

1=The rising and falling ramp times are in Asymmetric mode.

Table 28-12, "Asymmetric Breathing Mode Register Usage"

shows the application of the Stepsize and Interval registers to the

four segments of rising duty cycles and the four segments of fall-

ing duty cycles.

0=The rising and falling ramp times (as shown in Figure 28-2, "Breath-

ing LED Example") are in Symmetric mode. Table 28-11, "Sym-

metric Breathing Mode Register Usage" shows the application of

the Stepsize and Interval registers to the 8 segments of both ris-

ing and falling duty cycles.

R/W

VCC1_

RESET

15:8 WDT_RELOAD

The PWM Watchdog Timer counter reload value. On system reset, it

defaults to 14h, which corresponds to a 4 second Watchdog timeout

value.

R/W

14h

VCC1_

RESET

7 RESET

Writes of’1’ to this bit resets the PWM registers to their default val-

ues. This bit is self clearing.

Writes of ‘0’ to this bit have no effect.

W0b

VCC1_

RESET

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